| Message ID | 1310731501-13078-9-git-send-email-tarun.kanti@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Friday 15 July 2011 05:34 PM, Tarun Kanti DebBarma wrote: > The low-level read and write access routines wait on write-pending register > in posted mode to make sure that previous write is complete on respective > registers. This waiting is done in an infinite while loop. Now it is being > modified to use timeout instead. > > Signed-off-by: Tarun Kanti DebBarma<tarun.kanti@ti.com> > Reviewed-by: Varadarajan, Charulatha<charu@ti.com> > Acked-by: Cousson, Benoit<b-cousson@ti.com> > --- > arch/arm/plat-omap/include/plat/dmtimer.h | 34 ++++++++++++++++++++-------- > 1 files changed, 24 insertions(+), 10 deletions(-) > > diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h > index 53d5da6..6e34094 100644 > --- a/arch/arm/plat-omap/include/plat/dmtimer.h > +++ b/arch/arm/plat-omap/include/plat/dmtimer.h > @@ -36,6 +36,8 @@ > #include<linux/delay.h> > #include<linux/platform_device.h> > > +#include<plat/common.h> > + > #ifndef __ASM_ARCH_DMTIMER_H > #define __ASM_ARCH_DMTIMER_H > > @@ -230,6 +232,8 @@ int omap_dm_timers_active(void); > #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ > (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR<< WPSHIFT)) > > +#define MAX_WRITE_PEND_WAIT 10000 /* 10ms timeout delay */ Minor comment. Space out the comment with the tab or put it up. Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Regards Santosh
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index 53d5da6..6e34094 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h @@ -36,6 +36,8 @@ #include <linux/delay.h> #include <linux/platform_device.h> +#include <plat/common.h> + #ifndef __ASM_ARCH_DMTIMER_H #define __ASM_ARCH_DMTIMER_H @@ -230,6 +232,8 @@ int omap_dm_timers_active(void); #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) +#define MAX_WRITE_PEND_WAIT 10000 /* 10ms timeout delay */ + struct omap_dm_timer { unsigned long phys_base; int id; @@ -251,11 +255,16 @@ void omap_dm_timer_prepare(struct omap_dm_timer *timer); static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg, int posted, u8 func_offset) { - if (posted) - while (__raw_readl(base + - ((OMAP_TIMER_WRITE_PEND_REG + func_offset) & 0xff)) - & (reg >> WPSHIFT)) - cpu_relax(); + int i = 0; + + if (posted) { + omap_test_timeout(!(__raw_readl(base + + ((OMAP_TIMER_WRITE_PEND_REG + func_offset) & 0xff)) & + (reg >> WPSHIFT)), MAX_WRITE_PEND_WAIT, i); + + if (WARN_ON_ONCE(i == MAX_WRITE_PEND_WAIT)) + pr_err("read timeout.\n"); + } return __raw_readl(base + (reg & 0xff)); } @@ -263,11 +272,16 @@ static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg, static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val, int posted, u8 func_offset) { - if (posted) - while (__raw_readl(base + - ((OMAP_TIMER_WRITE_PEND_REG + func_offset) & 0xff)) - & (reg >> WPSHIFT)) - cpu_relax(); + int i = 0; + + if (posted) { + omap_test_timeout(!(__raw_readl(base + + ((OMAP_TIMER_WRITE_PEND_REG + func_offset) & 0xff)) & + (reg >> WPSHIFT)), MAX_WRITE_PEND_WAIT, i); + + if (WARN_ON(i == MAX_WRITE_PEND_WAIT)) + pr_err("write timeout.\n"); + } __raw_writel(val, base + (reg & 0xff)); }