From patchwork Mon Aug 15 20:28:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 1069252 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7FKaGpb011799 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 15 Aug 2011 20:36:37 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qt3s4-000700-UP; Mon, 15 Aug 2011 20:34:54 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Qt3o8-0000hT-KT; Mon, 15 Aug 2011 20:30:48 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Qt3mM-0000Dd-F4 for linux-arm-kernel@lists.infradead.org; Mon, 15 Aug 2011 20:29:00 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 6DEF56352; Mon, 15 Aug 2011 14:30:09 -0600 (MDT) Received: from localhost.localdomain (searspoint.nvidia.com [216.228.112.21]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id DAFCCE40EB; Mon, 15 Aug 2011 14:28:53 -0600 (MDT) From: Stephen Warren To: Grant Likely , Colin Cross , Erik Gilling , Olof Johansson Subject: [RFC PATCH v2 06/13] docs/dt: Document nvidia, tegra20-pinmux binding Date: Mon, 15 Aug 2011 14:28:13 -0600 Message-Id: <1313440100-17131-7-git-send-email-swarren@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1313440100-17131-1-git-send-email-swarren@nvidia.com> References: <1313440100-17131-1-git-send-email-swarren@nvidia.com> X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110815_162858_774623_B007F8A4 X-CRM114-Status: GOOD ( 14.45 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- Cc: Russell King , Sergei Shtylyov , Arnd Bergmann , Stephen Warren , Belisko Marek , devicetree-discuss@lists.ozlabs.org, linux-kernel@vger.kernel.org, Shawn Guo , linux-tegra@vger.kernel.org, Jamie Iles , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 15 Aug 2011 20:36:37 +0000 (UTC) Signed-off-by: Stephen Warren --- .../devicetree/bindings/pinmux/pinmux_nvidia.txt | 294 ++++++++++++++++++++ 1 files changed, 294 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt diff --git a/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt new file mode 100644 index 0000000..744e1b7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinmux/pinmux_nvidia.txt @@ -0,0 +1,294 @@ +NVIDIA Tegra 2 pinmux controller + +Required properties: +- compatible : "nvidia,tegra20-pinmux" + +Optional sub-nodes: +- nvidia,mux-groups : Mux group settings; see below. +- nvidia,drive-groups : Drive group settings; see below. + +nvidia,mux-groups sub-node: + +Each mux pin group is represented as a sub-node of the nvidia,mux-groups node. +The name of the sub-node should be the name of the mux pingroup. The following +names are valid: + + ata + atb + atc + atd + ate + cdev1 + cdev2 + crtp + csus + dap1 + dap2 + dap3 + dap4 + ddc + dta + dtb + dtc + dtd + dte + dtf + gma + gmb + gmc + gmd + gme + gpu + gpu7 + gpv + hdint + i2cp + irrx + irtx + kbca + kbcb + kbcc + kbcd + kbce + kbcf + lcsn + ld0 + ld1 + ld10 + ld11 + ld12 + ld13 + ld14 + ld15 + ld16 + ld17 + ld2 + ld3 + ld4 + ld5 + ld6 + ld7 + ld8 + ld9 + ldc + ldi + lhp0 + lhp1 + lhp2 + lhs + lm0 + lm1 + lpp + lpw0 + lpw1 + lpw2 + lsc0 + lsc1 + lsck + lsda + lsdi + lspi + lvp0 + lvp1 + lvs + owc + pmc + pta + rm + sdb + sdc + sdd + sdio1 + slxa + slxc + slxd + slxk + spdi + spdo + spia + spib + spic + spid + spie + spif + spig + spih + uaa + uab + uac + uad + uca + ucb + uda + ck32 + ddrc + pmca + pmcb + pmcc + pmcd + pmce + xm2c + xm2d + +Required subnode-properties: +- nvidia,function : A string containing the name of the pinmux function to + mux to the pingroup. The following names are valid; see the Tegra TRM to + determine which are valid for each pingroup: + + none (used for pingroups without muxing functionality) + ahb_clk + apb_clk + audio_sync + crt + dap1 + dap2 + dap3 + dap4 + dap5 + displaya + displayb + emc_test0_dll + emc_test1_dll + gmi + gmi_int + hdmi + i2c + i2c2 + i2c3 + ide + irda + kbc + mio + mipi_hs + nand + osc + owr + pcie + plla_out + pllc_out1 + pllm_out1 + pllp_out2 + pllp_out3 + pllp_out4 + pwm + pwr_intr + pwr_on + rtck + sdio1 + sdio2 + sdio3 + sdio4 + sflash + spdif + spi1 + spi2 + spi2_alt + spi3 + spi4 + trace + twc + uarta + uartb + uartc + uartd + uarte + ulpi + vi + vi_sensor_clk + xio + +optional subnode-properties: +- nvidia,pull-up : Boolean, apply Tegra's internal pull-up to the pin. +- nvidia,pull-down : Boolean, apply Tegra's internal pull-down to the pin. +- nvidia,tristate : Boolean, tristate the pin. Otherwise, drive it. + +If both nvidia,pull-up and nvidia,pull-down are specified, nvidia,pull-up +takes precedence. + +nvidia,drive-groups sub-node: + +Each drive pin group is represented as a sub-node of the nvidia,drive-groups +node. The name of the sub-node should be the name of the drive pingroup. The +following names are valid: + + ao1 + ao2 + at1 + at2 + cdev1 + cdev2 + csus + dap1 + dap2 + dap3 + dap4 + dbg + lcd1 + lcd2 + sdmmc2 + sdmmc3 + spi + uaa + uab + uart2 + uart3 + vi1 + vi2 + xm2a + xm2c + xm2d + xm2clk + memcomp + sdio1 + crt + ddc + gma + gmb + gmc + gmd + gme + owr + uad + +Required subnode-properties: +- nvidia,high-speed-mode : Boolean, enable high speed mode the pins. +- nvidia,schmitt : Boolean, enables Schmitt Trigger on the input. +- nvidia,drive-power : Integer, valid values 0-3. 0 is least power, 3 is + most power. Controls the drive power or current. See "Low Power Mode" + or "LPMD1" and "LPMD0" in the Tegra TRM. +- nvidia,pull-down-strength : Integer, valid values 0-31. Controls drive + strength. See "CAL_DRVDN" in the Tegra TRM. +- nvidia,pull-up-strength : Integer, valid values 0-31. Controls drive + strength. See "CAL_DRVUP" in the Tegra TRM. +- nvidia,slew_rate-rising : Integer, valid values 0-3. 0 is fastest, 3 is + slowest. See "DRVUP_SLWR" in the Tegra TRM. +- nvidia,slew_rate-falling : Integer, valid values 0-3. 0 is fastest, 3 is + slowest. See "DRVDN_SLWR" in the Tegra TRM. + +Example of a gpio-controller node: + + pinmux: pinmux@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = < 0x70000000 0xc00 >; + nvidia,mux-groups { + cdev1 { + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,function = "pllp_out4"; + nvidia,pull-down; + nvidia,tristate; + }; + }; + nvidia,drive-groups { + sdio1 { + nvidia,schmitt; + nvidia,drive-power = <1>; + nvidia,pull-down-strength = <31>; + nvidia,pull-up-strength = <31>; + nvidia,slew-rate-rising = <3>; + nvidia,slew-rate-falling = <3>; + }; + }; + }; +