From patchwork Mon Aug 22 15:36:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 1085862 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p7MFb4co006885 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 22 Aug 2011 15:37:30 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvWYI-0001Ha-Bq; Mon, 22 Aug 2011 15:36:38 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QvWYH-0001tP-Qb; Mon, 22 Aug 2011 15:36:37 +0000 Received: from va3ehsobe005.messaging.microsoft.com ([216.32.180.31] helo=VA3EHSOBE005.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvWXz-0001qU-QJ for linux-arm-kernel@lists.infradead.org; Mon, 22 Aug 2011 15:36:20 +0000 Received: from mail33-va3-R.bigfish.com (10.7.14.235) by VA3EHSOBE005.bigfish.com (10.7.40.25) with Microsoft SMTP Server id 14.1.225.22; Mon, 22 Aug 2011 15:36:18 +0000 Received: from mail33-va3 (localhost.localdomain [127.0.0.1]) by mail33-va3-R.bigfish.com (Postfix) with ESMTP id 4C65B14481F4; Mon, 22 Aug 2011 15:36:18 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275bhz2dh2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail33-va3 (localhost.localdomain [127.0.0.1]) by mail33-va3 (MessageSwitch) id 131402737866622_21480; Mon, 22 Aug 2011 15:36:18 +0000 (UTC) Received: from VA3EHSMHS015.bigfish.com (unknown [10.7.14.251]) by mail33-va3.bigfish.com (Postfix) with ESMTP id 00B7C1710059; Mon, 22 Aug 2011 15:36:17 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS015.bigfish.com (10.7.99.25) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 22 Aug 2011 15:36:14 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.323.2; Mon, 22 Aug 2011 10:36:13 -0500 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.240.183]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id p7MFa9c0011585; Mon, 22 Aug 2011 10:36:11 -0500 (CDT) From: Fabio Estevam To: Subject: [PATCH 2/2] ARM: mx25: Print silicon revision on boot Date: Mon, 22 Aug 2011 12:36:17 -0300 Message-ID: <1314027377-15915-2-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1314027377-15915-1-git-send-email-fabio.estevam@freescale.com> References: <1314027377-15915-1-git-send-email-fabio.estevam@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110822_113619_934540_4F1CD004 X-CRM114-Status: GOOD ( 21.09 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.180.31 listed in list.dnswl.org] Cc: Fabio Estevam , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Mon, 22 Aug 2011 15:37:53 +0000 (UTC) Silicon revision is useful information to have during kernel boot. Print the MX25 silicon revision. Signed-off-by: Fabio Estevam --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/clock-imx25.c | 3 ++ arch/arm/mach-imx/cpu-imx25.c | 40 +++++++++++++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mx25.h | 5 ++++ 4 files changed, 49 insertions(+), 1 deletions(-) create mode 100644 arch/arm/mach-imx/cpu-imx25.c diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e9eb36d..0a5332c 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o -obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o +obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o ehci-imx25.o cpu-imx25.o obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c index b919ad8..d20cbfc 100644 --- a/arch/arm/mach-imx/clock-imx25.c +++ b/arch/arm/mach-imx/clock-imx25.c @@ -330,6 +330,9 @@ int __init mx25_clocks_init(void) __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0), CRM_BASE + 0x64); + clk_enable(&iim_clk); + mx25_read_cpu_rev(); + mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); return 0; diff --git a/arch/arm/mach-imx/cpu-imx25.c b/arch/arm/mach-imx/cpu-imx25.c new file mode 100644 index 0000000..0e7b26e --- /dev/null +++ b/arch/arm/mach-imx/cpu-imx25.c @@ -0,0 +1,40 @@ +/* + * MX25 CPU type detection + * + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include + +unsigned int mx25_cpu_rev; +EXPORT_SYMBOL(mx25_cpu_rev); + +void __init mx25_read_cpu_rev(void) +{ + u32 rev; + char *srev; + + rev = __raw_readl(MX25_IO_ADDRESS(MX25_IIM_BASE_ADDR + MXC_IIMSREV)); + switch (rev) { + case 0x00: + mx25_cpu_rev = IMX_CHIP_REVISION_1_0; + srev = IMX_CHIP_REVISION_1_0_STRING; + break; + case 0x01: + mx25_cpu_rev = IMX_CHIP_REVISION_1_1; + srev = IMX_CHIP_REVISION_1_1_STRING; + break; + default: + mx25_cpu_rev = IMX_CHIP_REVISION_UNKNOWN; + srev = IMX_CHIP_REVISION_UNKNOWN_STRING; + } + + pr_info("CPU identified as i.MX25, silicon rev %s\n", srev); +} diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h index 087cd7a..40ddcda 100644 --- a/arch/arm/plat-mxc/include/mach/mx25.h +++ b/arch/arm/plat-mxc/include/mach/mx25.h @@ -41,6 +41,7 @@ #define MX25_SSI2_BASE_ADDR 0x50014000 #define MX25_SSI1_BASE_ADDR 0x50034000 #define MX25_NFC_BASE_ADDR 0xbb000000 +#define MX25_IIM_BASE_ADDR 0x53ff0000 #define MX25_DRYICE_BASE_ADDR 0x53ffc000 #define MX25_ESDHC1_BASE_ADDR 0x53fb4000 #define MX25_ESDHC2_BASE_ADDR 0x53fb8000 @@ -104,4 +105,8 @@ #define MX25_DMA_REQ_SSI1_RX0 28 #define MX25_DMA_REQ_SSI1_TX0 29 +#ifndef __ASSEMBLY__ +extern void mx25_read_cpu_rev(void); +#endif + #endif /* ifndef __MACH_MX25_H__ */