From patchwork Mon Aug 22 15:52:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 1085872 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter2.kernel.org (8.14.4/8.14.4) with ESMTP id p7MFr42U002202 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Mon, 22 Aug 2011 15:53:25 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvWnu-0003FS-5d; Mon, 22 Aug 2011 15:52:46 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QvWnt-00020E-ND; Mon, 22 Aug 2011 15:52:45 +0000 Received: from db3ehsobe001.messaging.microsoft.com ([213.199.154.139] helo=DB3EHSOBE001.bigfish.com) by canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QvWnp-0001zv-I5 for linux-arm-kernel@lists.infradead.org; Mon, 22 Aug 2011 15:52:43 +0000 Received: from mail75-db3-R.bigfish.com (10.3.81.253) by DB3EHSOBE001.bigfish.com (10.3.84.21) with Microsoft SMTP Server id 14.1.225.22; Mon, 22 Aug 2011 15:52:37 +0000 Received: from mail75-db3 (localhost.localdomain [127.0.0.1]) by mail75-db3-R.bigfish.com (Postfix) with ESMTP id BC8E51BD8261; Mon, 22 Aug 2011 15:52:37 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h62h) X-Spam-TCS-SCL: 1:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail75-db3 (localhost.localdomain [127.0.0.1]) by mail75-db3 (MessageSwitch) id 1314028357607381_13392; Mon, 22 Aug 2011 15:52:37 +0000 (UTC) Received: from DB3EHSMHS002.bigfish.com (unknown [10.3.81.246]) by mail75-db3.bigfish.com (Postfix) with ESMTP id 863B64004B; Mon, 22 Aug 2011 15:52:37 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS002.bigfish.com (10.3.87.102) with Microsoft SMTP Server (TLS) id 14.1.225.22; Mon, 22 Aug 2011 15:52:36 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server id 14.1.323.2; Mon, 22 Aug 2011 10:52:34 -0500 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.240.183]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p7MFqVYq010859; Mon, 22 Aug 2011 10:52:32 -0500 (CDT) From: Fabio Estevam To: Subject: [PATCH] ARM: mx27: Print silicon revision on boot Date: Mon, 22 Aug 2011 12:52:41 -0300 Message-ID: <1314028361-25622-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.7.1 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110822_115241_856257_D2168D22 X-CRM114-Status: GOOD ( 14.33 ) X-Spam-Score: -0.7 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-0.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.139 listed in list.dnswl.org] Cc: Fabio Estevam , kernel@pengutronix.de X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter2.kernel.org [140.211.167.43]); Mon, 22 Aug 2011 15:53:26 +0000 (UTC) Silicon revision is useful information to have during kernel boot. Print the MX27 silicon revision. Signed-off-by: Fabio Estevam --- arch/arm/mach-imx/clock-imx27.c | 1 + arch/arm/mach-imx/cpu-imx27.c | 23 +++++++++++++++++++++++ arch/arm/plat-mxc/include/mach/mx27.h | 1 + 3 files changed, 25 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c index 6912b82..2858137 100644 --- a/arch/arm/mach-imx/clock-imx27.c +++ b/arch/arm/mach-imx/clock-imx27.c @@ -756,6 +756,7 @@ int __init mx27_clocks_init(unsigned long fref) clk_enable(&uart1_clk); #endif + mx27_read_cpu_rev(); mxc_timer_init(&gpt1_clk, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c index 3b117be..8f6495e 100644 --- a/arch/arm/mach-imx/cpu-imx27.c +++ b/arch/arm/mach-imx/cpu-imx27.c @@ -74,3 +74,26 @@ int mx27_revision(void) return cpu_silicon_rev; } EXPORT_SYMBOL(mx27_revision); + +void __init mx27_read_cpu_rev(void) +{ + u32 rev; + char *srev; + + rev = mx27_revision(); + switch (rev) { + case IMX_CHIP_REVISION_1_0: + srev = IMX_CHIP_REVISION_1_0_STRING; + break; + case IMX_CHIP_REVISION_2_0: + srev = IMX_CHIP_REVISION_2_0_STRING; + break; + case IMX_CHIP_REVISION_2_1: + srev = IMX_CHIP_REVISION_2_1_STRING; + break; + default: + srev = IMX_CHIP_REVISION_UNKNOWN_STRING; + } + + pr_info("CPU identified as i.MX27, silicon rev %s\n", srev); +} diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 1dc1c52..76edec7 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h @@ -246,6 +246,7 @@ static inline void mx27_setup_weimcs(size_t cs, #ifndef __ASSEMBLY__ extern int mx27_revision(void); +extern void mx27_read_cpu_rev(void); #endif #endif /* ifndef __MACH_MX27_H__ */