From patchwork Fri Sep 2 02:59:11 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolas Pitre X-Patchwork-Id: 1121192 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p8232JPH003791 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Fri, 2 Sep 2011 03:02:40 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1QzK11-0001To-Nj; Fri, 02 Sep 2011 03:02:01 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QzK01-0000HX-Rn; Fri, 02 Sep 2011 03:00:57 +0000 Received: from relais.videotron.ca ([24.201.245.36]) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1QzJyf-0008GY-7h for linux-arm-kernel@lists.infradead.org; Fri, 02 Sep 2011 02:59:35 +0000 Received: from yoda.home ([66.130.28.92]) by VL-VM-MR006.ip.videotron.ca (Oracle Communications Messaging Exchange Server 7u4-22.01 64bit (built Apr 21 2011)) with ESMTP id <0LQV00B15KAWMTB0@VL-VM-MR006.ip.videotron.ca> for linux-arm-kernel@lists.infradead.org; Thu, 01 Sep 2011 22:59:20 -0400 (EDT) Received: from xanadu.home (xanadu.home [192.168.2.2]) by yoda.home (Postfix) with ESMTP id E696A2148D for ; Thu, 01 Sep 2011 22:59:19 -0400 (EDT) From: Nicolas Pitre To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/6] ARM: mach-omap2: clean up debug-macro.S Date: Thu, 01 Sep 2011 22:59:11 -0400 Message-id: <1314932353-24813-5-git-send-email-nico@fluxnic.net> X-Mailer: git-send-email 1.7.4 In-reply-to: <1314932353-24813-1-git-send-email-nico@fluxnic.net> References: <1314932353-24813-1-git-send-email-nico@fluxnic.net> X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110901_225933_505001_FA0FA83A X-CRM114-Status: GOOD ( 16.29 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [24.201.245.36 listed in list.dnswl.org] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 02 Sep 2011 03:02:40 +0000 (UTC) This achieves two goals: 1) Get rid of omap_uart_v2p() and omap_uart_p2v() which were the last users of PLAT_PHYS_OFFSET. 2) Remove the probing of the M bit in the CP15 control reg and make the access to the .data variables completely position independent. There is a catch though: the busyuart macro needs to know where the LSR register is which might be at a different offset depending on the hardware. Given that this macro is given only two registers and that one of them must be preserved, the trick is to always pass the LSR register address around, and deduce the base address for the THR register by masking out the LSR offset in senduart instead. Signed-off-by: Nicolas Pitre --- arch/arm/mach-omap2/include/mach/debug-macro.S | 68 ++++++++++------------- 1 files changed, 30 insertions(+), 38 deletions(-) diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index 745e2ff..2f32abb 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -13,15 +13,10 @@ #include -#include - #include #define UART_OFFSET(addr) ((addr) & 0x00ffffff) -#define omap_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET) -#define omap_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET) - .pushsection .data omap_uart_phys: .word 0 omap_uart_virt: .word 0 @@ -37,13 +32,13 @@ omap_uart_lsr: .word 0 .macro addruart, rp, rv, tmp /* Use omap_uart_phys/virt if already configured */ -10: mrc p15, 0, \rp, c1, c0 - tst \rp, #1 @ MMU enabled? - ldreq \rp, =omap_uart_v2p(omap_uart_phys) @ MMU disabled - ldrne \rp, =omap_uart_phys @ MMU enabled - add \rv, \rp, #4 @ omap_uart_virt - ldr \rp, [\rp, #0] - ldr \rv, [\rv, #0] +10: adr \rp, 11f @ get effective addr of 11f + ldr \rv, [\rp] @ get absolute addr of 11f + sub \rv, \rv, \rp @ offset between the two + ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys + sub \tmp, \rp, \rv @ make it effective + ldr \rp, [\tmp, #0] @ omap_uart_phys + ldr \rv, [\tmp, #4] @ omap_uart_virt cmp \rp, #0 @ is port configured? cmpne \rv, #0 bne 99f @ already configured @@ -105,50 +100,47 @@ omap_uart_lsr: .word 0 b 98f 83: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) b 98f + 95: ldr \rp, =ZOOM_UART_BASE - mrc p15, 0, \rv, c1, c0 - tst \rv, #1 @ MMU enabled? - ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled - ldrne \rv, =omap_uart_phys @ MMU enabled - str \rp, [\rv, #0] + str \rp, [\tmp, #0] @ omap_uart_phys ldr \rp, =ZOOM_UART_VIRT - add \rv, \rv, #4 @ omap_uart_virt - str \rp, [\rv, #0] + str \rp, [\tmp, #4] @ omap_uart_virt mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT) - add \rv, \rv, #4 @ omap_uart_lsr - str \rp, [\rv, #0] + str \rp, [\tmp, #8] @ omap_uart_lsr b 10b /* Store both phys and virt address for the uart */ 98: add \rp, \rp, #0x48000000 @ phys base - mrc p15, 0, \rv, c1, c0 - tst \rv, #1 @ MMU enabled? - ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled - ldrne \rv, =omap_uart_phys @ MMU enabled - str \rp, [\rv, #0] + str \rp, [\tmp, #0] @ omap_uart_phys sub \rp, \rp, #0x48000000 @ phys base add \rp, \rp, #0xfa000000 @ virt base - add \rv, \rv, #4 @ omap_uart_virt - str \rp, [\rv, #0] + str \rp, [\tmp, #4] @ omap_uart_virt mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) - add \rv, \rv, #4 @ omap_uart_lsr - str \rp, [\rv, #0] + str \rp, [\tmp, #8] @ omap_uart_lsr b 10b -99: + + .align +11: .word . + .word omap_uart_phys + .ltorg + +99: /* Pass the UART_LSR reg address */ + ldr \tmp, [\tmp, #8] @ omap_uart_lsr + add \rp, \rp, \tmp + add \rv, \rv, \tmp .endm .macro senduart,rd,rx - strb \rd, [\rx] + orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset + bic \rx, \rx, #0xff @ get base (THR) reg address + strb \rd, [\rx] @ send lower byte of rd + orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR) + bic \rd, \rd, #(0xff << 24) @ restore original rd .endm .macro busyuart,rd,rx -1001: mrc p15, 0, \rd, c1, c0 - tst \rd, #1 @ MMU enabled? - ldreq \rd, =omap_uart_v2p(omap_uart_lsr) @ MMU disabled - ldrne \rd, =omap_uart_lsr @ MMU enabled - ldr \rd, [\rd, #0] - ldrb \rd, [\rx, \rd] +1001: ldrb \rd, [\rx] @ rx contains UART_LSR address and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) bne 1001b