From patchwork Sun Sep 4 09:01:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1123532 Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p8492iYc032258 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO) for ; Sun, 4 Sep 2011 09:03:05 GMT Received: from canuck.infradead.org ([2001:4978:20e::1]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1R08aE-0004ke-Bb; Sun, 04 Sep 2011 09:01:42 +0000 Received: from localhost ([127.0.0.1] helo=canuck.infradead.org) by canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1R08aE-00073L-0D; Sun, 04 Sep 2011 09:01:42 +0000 Received: from eu1sys200aog116.obsmtp.com ([207.126.144.141]) by canuck.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1R08a8-000732-Rx for linux-arm-kernel@lists.infradead.org; Sun, 04 Sep 2011 09:01:39 +0000 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob116.postini.com ([207.126.147.11]) with SMTP ID DSNKTmM+ZVW6HmWvbWUPxUaLfBCd9j6Dv3n/@postini.com; Sun, 04 Sep 2011 09:01:36 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A93B1B9; Sun, 4 Sep 2011 09:01:21 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2B13D13E5; Sun, 4 Sep 2011 09:01:21 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 0050EA8074; Sun, 4 Sep 2011 11:01:17 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Sun, 4 Sep 2011 11:01:20 +0200 From: Linus Walleij To: Subject: [PATCH] ARM: l2x0: make sure I&D are not locked down on init Date: Sun, 4 Sep 2011 11:01:12 +0200 Message-ID: <1315126872-3290-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20110904_050137_152941_862BF93A X-CRM114-Status: GOOD ( 14.59 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.1 on canuck.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.141 listed in list.dnswl.org] Cc: Rabin Vincent , Srinidhi Kasagar , Catalin Marinas , Linus Walleij , Will Deacon , Lee Jones , Adrian Bunk X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Sun, 04 Sep 2011 09:03:06 +0000 (UTC) From: Linus Walleij Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state. Cc: Srinidhi Kasagar Cc: Rabin Vincent Cc: Adrian Bunk Cc: Rob Herring Cc: Catalin Marinas Cc: Will Deacon Reported-by: Jan Rinze Tested-by: Robert Marklund Signed-off-by: Linus Walleij --- arch/arm/mm/cache-l2x0.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 44c0867..b03c835 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -338,6 +338,10 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) writel_relaxed(1, l2x0_base + L2X0_CTRL); } + /* Make sure that I&D is not locked down when starting */ + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D); + writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I); + outer_cache.inv_range = l2x0_inv_range; outer_cache.clean_range = l2x0_clean_range; outer_cache.flush_range = l2x0_flush_range;