From patchwork Tue Jul 24 01:09:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Cyril Chemparathy X-Patchwork-Id: 1415471 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 7CC273FC71 for ; Thu, 6 Sep 2012 15:00:17 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T9dSw-00082W-Bp; Thu, 06 Sep 2012 14:54:00 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1StTdC-0002ZE-JF for linux-arm-kernel@lists.infradead.org; Tue, 24 Jul 2012 01:10:09 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id q6O19e5p027114; Mon, 23 Jul 2012 20:09:40 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6O19euP010270; Mon, 23 Jul 2012 20:09:40 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Mon, 23 Jul 2012 20:09:39 -0500 Received: from ares-ubuntu.am.dhcp.ti.com (ares-ubuntu.am.dhcp.ti.com [158.218.103.17]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q6O19dBS024600; Mon, 23 Jul 2012 20:09:39 -0500 Received: from a0875269 by ares-ubuntu.am.dhcp.ti.com with local (Exim 4.76) (envelope-from ) id 1StTd5-0002Uc-Et; Mon, 23 Jul 2012 21:09:39 -0400 From: Cyril Chemparathy To: Subject: [RFC 16/23] ARM: LPAE: accomodate >32-bit addresses for page table base Date: Mon, 23 Jul 2012 21:09:18 -0400 Message-ID: <1343092165-9470-17-git-send-email-cyril@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343092165-9470-1-git-send-email-cyril@ti.com> References: <1343092165-9470-1-git-send-email-cyril@ti.com> MIME-Version: 1.0 X-Bad-Reply: References and In-Reply-To but no 'Re:' in Subject. X-Spam-Note: CRM114 invocation failed X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-Mailman-Approved-At: Thu, 06 Sep 2012 10:43:36 -0400 Cc: nico@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, Vitaly Andrianov , Cyril Chemparathy X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch redefines the early boot time use of the R4 register to steal a few low order bits (ARCH_PGD_SHIFT bits), allowing for up to 38-bit physical addresses. This is probably not the best means to the end, and a better alternative may be to modify the head.S register allocations to fit in full register pairs for pgdir and swapper_pg_dir. However, squeezing out these extra registers seemed to be a far greater pain than squeezing out a few low order bits from the page table addresses. Signed-off-by: Cyril Chemparathy Signed-off-by: Vitaly Andrianov --- arch/arm/include/asm/cache.h | 9 +++++++++ arch/arm/kernel/head.S | 7 +++++-- arch/arm/kernel/smp.c | 11 +++++++++-- arch/arm/mm/proc-arm1026.S | 2 ++ arch/arm/mm/proc-mohawk.S | 2 ++ arch/arm/mm/proc-v6.S | 2 ++ arch/arm/mm/proc-v7-2level.S | 2 ++ arch/arm/mm/proc-v7-3level.S | 7 +++++++ arch/arm/mm/proc-v7.S | 1 + arch/arm/mm/proc-xsc3.S | 2 ++ 10 files changed, 41 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 75fe66b..986480c 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -17,6 +17,15 @@ #define ARCH_DMA_MINALIGN L1_CACHE_BYTES /* + * Minimum guaranted alignment in pgd_alloc(). The page table pointers passed + * around in head.S and proc-*.S are shifted by this amount, in order to + * leave spare high bits for systems with physical address extension. This + * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but + * gives us about 38-bits or so. + */ +#define ARCH_PGD_SHIFT L1_CACHE_SHIFT + +/* * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. */ #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 692e57f..6fe1c40 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -22,6 +22,7 @@ #include #include #include +#include #ifdef CONFIG_DEBUG_LL #include @@ -160,7 +161,7 @@ ENDPROC(stext) * * Returns: * r0, r3, r5-r7 corrupted - * r4 = physical page table address + * r4 = page table (see ARCH_PGD_SHIFT in asm/cache.h) */ __create_page_tables: pgtbl r4, r8 @ page table address @@ -320,6 +321,7 @@ __create_page_tables: #ifdef CONFIG_ARM_LPAE sub r4, r4, #0x1000 @ point to the PGD table #endif + mov r4, r4, lsr #ARCH_PGD_SHIFT mov pc, lr ENDPROC(__create_page_tables) .ltorg @@ -392,7 +394,7 @@ __secondary_data: * r0 = cp#15 control register * r1 = machine ID * r2 = atags or dtb pointer - * r4 = page table pointer + * r4 = page table (see ARCH_PGD_SHIFT in asm/cache.h) * r9 = processor ID * r13 = *virtual* address to jump to upon completion */ @@ -422,6 +424,7 @@ __enable_mmu: @ has the processor setup already programmed the page table pointer? adds r5, r4, #1 beq __turn_mmu_on @ yes! + mov r4, r4, lsl #ARCH_PGD_SHIFT mcr p15, 0, r4, c2, c0, 0 @ load page table pointer b __turn_mmu_on ENDPROC(__enable_mmu) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 2c7217d..e41e1be 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -42,6 +42,7 @@ #include #include #include +#include /* * as from 2.5, kernels no longer have an init_tasks structure @@ -62,6 +63,7 @@ static DECLARE_COMPLETION(cpu_running); int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) { + phys_addr_t pgdir; int ret; /* @@ -69,8 +71,13 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle) * its stack and the page tables. */ secondary_data.stack = task_stack_page(idle) + THREAD_START_SP; - secondary_data.pgdir = virt_to_phys(idmap_pgd); - secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir); + + pgdir = virt_to_phys(idmap_pgd); + secondary_data.pgdir = pgdir >> ARCH_PGD_SHIFT; + + pgdir = virt_to_phys(swapper_pg_dir); + secondary_data.swapper_pg_dir = pgdir >> ARCH_PGD_SHIFT; + __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data)); outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1)); diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index c28070e..4556f77 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -22,6 +22,7 @@ #include #include #include +#include #include "proc-macros.S" @@ -403,6 +404,7 @@ __arm1026_setup: mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 + mov r4, r4, lsl #ARCH_PGD_SHIFT mcr p15, 0, r4, c2, c0 @ load page table pointer mvn r4, #0 @ do not set page table pointer #endif diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index a26303c..13fcc67 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -28,6 +28,7 @@ #include #include #include +#include #include "proc-macros.S" /* @@ -388,6 +389,7 @@ __mohawk_setup: mcr p15, 0, r0, c7, c7 @ invalidate I,D caches mcr p15, 0, r0, c7, c10, 4 @ drain write buffer mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs + mov r4, r4, lsl #ARCH_PGD_SHIFT orr r4, r4, #0x18 @ cache the page table in L2 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer mvn r4, #0 @ do not set page table pointer diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 872156e..4751be7 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -17,6 +17,7 @@ #include #include #include +#include #include "proc-macros.S" @@ -206,6 +207,7 @@ __v6_setup: #ifdef CONFIG_MMU mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs mcr p15, 0, r0, c2, c0, 2 @ TTB control register + mov r4, r4, lsl #ARCH_PGD_SHIFT ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) ALT_UP(orr r4, r4, #TTB_FLAGS_UP) ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S index cc78c0c..f4bc63b 100644 --- a/arch/arm/mm/proc-v7-2level.S +++ b/arch/arm/mm/proc-v7-2level.S @@ -143,8 +143,10 @@ ENDPROC(cpu_v7_set_pte_ext) */ .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp mcr p15, 0, \zero, c2, c0, 2 @ TTB control register + mov \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT ALT_SMP(orr \ttbr0, \ttbr0, #TTB_FLAGS_SMP) ALT_UP(orr \ttbr0, \ttbr0, #TTB_FLAGS_UP) + mov \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP) ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP) mcr p15, 0, \ttbr0, c2, c0, 0 @ load TTB0 diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S index 5e3bed1..33f322a 100644 --- a/arch/arm/mm/proc-v7-3level.S +++ b/arch/arm/mm/proc-v7-3level.S @@ -103,6 +103,7 @@ ENDPROC(cpu_v7_set_pte_ext) */ .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address + mov \tmp, \tmp, lsr #ARCH_PGD_SHIFT cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET? (branch below) mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register orr \tmp, \tmp, #TTB_EAE @@ -122,8 +123,14 @@ ENDPROC(cpu_v7_set_pte_ext) */ orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR + mov \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits + mov \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT @ lower bits addls \ttbr1, \ttbr1, #TTBR1_OFFSET mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1 + mov \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT) @ upper bits + mov \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT @ lower bits + mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0 + mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1 mcrr p15, 0, \ttbr0, \zero, c2 @ load TTBR0 .endm diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 8850194..443f602 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -16,6 +16,7 @@ #include #include #include +#include #include "proc-macros.S" diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index db3836b..a43a07d 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -32,6 +32,7 @@ #include #include #include +#include #include "proc-macros.S" /* @@ -453,6 +454,7 @@ __xsc3_setup: mcr p15, 0, ip, c7, c10, 4 @ data write barrier mcr p15, 0, ip, c7, c5, 4 @ prefetch flush mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs + mov r4, r4, lsl #ARCH_PGD_SHIFT orr r4, r4, #0x18 @ cache the page table in L2 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer mvn r4, #0 @ do not set page table pointer