Message ID | 1344461278-28245-5-git-send-email-arnd@arndb.de (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On Wed, 8 Aug 2012, Arnd Bergmann wrote: > The Linaro cross toolchain and probably others nowadays default to > building in THUMB2 mode. When building a kernel for a CPU that does > not support THUMB2, the compiler complains about incorrect flags. > We can work around this by setting -marm for all non-T2 builds. > > Without this patch, building assabet_defconfig results in: > > usr/initramfs_data.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default] > arch/arm/nwfpe/entry.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default] > firmware/cis/PCMLM28.cis.gen.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default] > (and many more) > > Signed-off-by: Arnd Bergmann <arnd@arndb.de> > Cc: Russell King <rmk+kernel@arm.linux.org.uk> > Cc: Dave Martin <dave.martin@linaro.org> > --- > arch/arm/Makefile | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > index 30eae87..b4c2296 100644 > --- a/arch/arm/Makefile > +++ b/arch/arm/Makefile > @@ -111,6 +111,9 @@ AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb > ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y) > CFLAGS_MODULE +=-fno-optimize-sibling-calls > endif > +else > +CFLAGS_THUMB2 :=-marm > +AFLAGS_THUMB2 :=-marm CFLAGS_THUMB2 should probably be renamed to something more appropriate in this case, e.g. CFLAGS_MODE. Nicolas
On Thu, Aug 09, 2012 at 05:12:58PM -0400, Nicolas Pitre wrote: > CFLAGS_THUMB2 should probably be renamed to something more appropriate > in this case, e.g. CFLAGS_MODE. CFLAGS_ISA would be more relevant to it, because it's selecting the instruction set.
On Thu, 9 Aug 2012, Russell King - ARM Linux wrote: > On Thu, Aug 09, 2012 at 05:12:58PM -0400, Nicolas Pitre wrote: > > CFLAGS_THUMB2 should probably be renamed to something more appropriate > > in this case, e.g. CFLAGS_MODE. > > CFLAGS_ISA would be more relevant to it, because it's selecting the > instruction set. Agreed. This particular TLA escaped my mind somehow. Nicolas
On Thu, Aug 09, 2012 at 05:22:30PM -0400, Nicolas Pitre wrote: > On Thu, 9 Aug 2012, Russell King - ARM Linux wrote: > > > On Thu, Aug 09, 2012 at 05:12:58PM -0400, Nicolas Pitre wrote: > > > CFLAGS_THUMB2 should probably be renamed to something more appropriate > > > in this case, e.g. CFLAGS_MODE. > > > > CFLAGS_ISA would be more relevant to it, because it's selecting the > > instruction set. > > Agreed. This particular TLA escaped my mind somehow. Seems fair enough. It doesn't quite match the official architectural terminology, but it clear enough what it means, and less cumbersome than the alternatives. Best not to use MODE though. That word is way too overloaded. ---Dave
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 30eae87..b4c2296 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -111,6 +111,9 @@ AFLAGS_THUMB2 :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb ifeq ($(CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11),y) CFLAGS_MODULE +=-fno-optimize-sibling-calls endif +else +CFLAGS_THUMB2 :=-marm +AFLAGS_THUMB2 :=-marm endif # Need -Uarm for gcc < 3.x
The Linaro cross toolchain and probably others nowadays default to building in THUMB2 mode. When building a kernel for a CPU that does not support THUMB2, the compiler complains about incorrect flags. We can work around this by setting -marm for all non-T2 builds. Without this patch, building assabet_defconfig results in: usr/initramfs_data.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default] arch/arm/nwfpe/entry.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default] firmware/cis/PCMLM28.cis.gen.S:1:0: warning: target CPU does not support THUMB instructions [enabled by default] (and many more) Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Dave Martin <dave.martin@linaro.org> --- arch/arm/Makefile | 3 +++ 1 file changed, 3 insertions(+)