From patchwork Fri Aug 10 21:57:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Vaswani X-Patchwork-Id: 1306731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id F2AA53FC66 for ; Fri, 10 Aug 2012 22:01:35 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1SzxDF-0003Bv-7Q; Fri, 10 Aug 2012 21:57:45 +0000 Received: from wolverine01.qualcomm.com ([199.106.114.254]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1SzxDB-0003Bh-VR for linux-arm-kernel@lists.infradead.org; Fri, 10 Aug 2012 21:57:42 +0000 X-IronPort-AV: E=McAfee;i="5400,1158,6799"; a="224141452" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine01.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 10 Aug 2012 14:57:40 -0700 Received: from codeaurora.org (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 7F8BE10004D4; Fri, 10 Aug 2012 14:57:39 -0700 (PDT) From: Rohit Vaswani To: marc.zyngier@arm.com, Russell King Subject: [PATCH 1/2] ARM: local timers: Unmask interrupt before new TVAL is set Date: Fri, 10 Aug 2012 14:57:34 -0700 Message-Id: <1344635854-5033-1-git-send-email-rvaswani@codeaurora.org> X-Mailer: git-send-email 1.7.8.3 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.254 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-msm@vger.kernel.org, Rohit Vaswani , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Level triggered interrupt is deasserted when a new TVAL is written only when the interrupt is unmasked. Make sure that the interrupt is unmasked in CTL register before TVAL is written. If this order is not followed, there are chances that on some hardware you would not receive any timer interrupts. Signed-off-by: Rohit Vaswani --- arch/arm/kernel/arch_timer.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c index dd58035..1d0d9df 100644 --- a/arch/arm/kernel/arch_timer.c +++ b/arch/arm/kernel/arch_timer.c @@ -126,8 +126,8 @@ static int arch_timer_set_next_event(unsigned long evt, ctrl |= ARCH_TIMER_CTRL_ENABLE; ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; - arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); return 0; }