From patchwork Mon Aug 20 05:49:37 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 1346711 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 7507540210 for ; Mon, 20 Aug 2012 05:52:24 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T3KrQ-0006Ov-4t; Mon, 20 Aug 2012 05:49:12 +0000 Received: from mail-pz0-f49.google.com ([209.85.210.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T3KrL-0006Oh-Dd for linux-arm-kernel@lists.infradead.org; Mon, 20 Aug 2012 05:49:08 +0000 Received: by dajq27 with SMTP id q27so2084032daj.36 for ; Sun, 19 Aug 2012 22:49:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer; bh=KCH2XHsOy3ySxq1N4RryX0hBSAW5yOiZ6Y+baPmD0w4=; b=Qyywytpj6tixgVBzbWXPfO0w6bXH93dnh6xbV961BdXuoMlyZNs1IEUveAraGD0wzB Zl0f8nqjj5tXjW097JJanw2CUc57ntFqehzpjzj8DTpZnGqIjbmC0Z8vavq1CdDIrrVE w6TLN2ixro2xYZwpAvVdnoDl1K5cnn/11viQKxQBvn4M8x71qCZvKLzD7qvM1DPfXB4j 9wDOkpM1ziJuORXI/XS4cB/evfNr4wFsorpM1tycOpx44F484qw3MScREy6bCy/MoesN ob+aGWNI5AYsOuwa/M8l5T5lZkumrzqUPKqSCoicYTvzHItiRTBWk4TQvzGPWA6nwILu rXJw== Received: by 10.66.76.106 with SMTP id j10mr27011239paw.51.1345441742032; Sun, 19 Aug 2012 22:49:02 -0700 (PDT) Received: from localhost ([221.239.195.16]) by mx.google.com with ESMTPS id sj5sm10398655pbc.30.2012.08.19.22.48.58 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 19 Aug 2012 22:49:01 -0700 (PDT) From: Haojian Zhuang To: chao.xie@marvell.com, zonque@gmail.com, linux-arm-kernel@lists.infradead.org, arnd@arndb.de Subject: [PATCH 1/3] ARM: pxa: append the definition of CKENC Date: Mon, 20 Aug 2012 13:49:37 +0800 Message-Id: <1345441779-22632-1-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.7.9.5 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (haojian.zhuang[at]gmail.com) -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.210.49 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Signed-off-by: Haojian Zhuang --- arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index 207ecb4..f4d48d2 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h @@ -131,6 +131,7 @@ #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ #define CKENA __REG(0x4134000C) /* A Clock Enable Register */ #define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define CKENC __REG(0x41340024) /* C Clock Enable Register */ #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */