From patchwork Mon Aug 27 21:18:39 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 1378441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 992923FC66 for ; Mon, 27 Aug 2012 21:23:17 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T66iA-0001mL-JU; Mon, 27 Aug 2012 21:19:06 +0000 Received: from wolverine02.qualcomm.com ([199.106.114.251]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T66i6-0001m7-6Y for linux-arm-kernel@lists.infradead.org; Mon, 27 Aug 2012 21:19:03 +0000 X-IronPort-AV: E=McAfee;i="5400,1158,6817"; a="227730827" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 27 Aug 2012 14:18:42 -0700 Received: from sboyd-linux.qualcomm.com (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id D1AA110004B6; Mon, 27 Aug 2012 14:18:41 -0700 (PDT) From: Stephen Boyd To: Will Deacon Subject: [PATCH] ARM: MSM: Implement read_current_timer for msm timers Date: Mon, 27 Aug 2012 14:18:39 -0700 Message-Id: <1346102319-24497-1-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 1.7.12.70.g851f7e6 In-Reply-To: <1345817604-9004-2-git-send-email-will.deacon@arm.com> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.251 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-msm@vger.kernel.org, shinya.kuribayashi.px@renesas.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jonathan Austin X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Setup the same timer used as the clocksource to be used as the read_current_timer implementation. This allows us to support a stable udelay implementation on MSMs where it's possible for the CPUs to scale speeds independently of one another. Signed-off-by: Stephen Boyd --- I have some patches to send that add DT support to the MSM timer that this conflicts with slightly. I'm not too concerned though, but we may want to decide what tree this goes through when I send out those patches. arch/arm/mach-msm/timer.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 81280825..1997ab1 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -172,6 +173,16 @@ static notrace u32 msm_sched_clock_read(void) return msm_clocksource.read(&msm_clocksource); } +static int msm_read_current_timer(unsigned long *timer_val) +{ + *timer_val = msm_clocksource.read(&msm_clocksource); + return 0; +} + +static struct delay_timer msm_delay_timer = { + .read_current_timer = msm_read_current_timer, +}; + static void __init msm_timer_init(void) { struct clock_event_device *ce = &msm_clockevent; @@ -240,6 +251,8 @@ err: pr_err("clocksource_register failed\n"); setup_sched_clock(msm_sched_clock_read, cpu_is_msm7x01() ? 32 - MSM_DGT_SHIFT : 32, dgt_hz); + msm_delay_timer.freq = dgt_hz; + register_current_timer_delay(&msm_delay_timer); } struct sys_timer msm_timer = {