From patchwork Fri Aug 31 00:00:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 1390431 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id A9B80DF264 for ; Fri, 31 Aug 2012 00:03:03 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1T7Eez-00009m-70; Fri, 31 Aug 2012 00:00:29 +0000 Received: from wolverine02.qualcomm.com ([199.106.114.251]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1T7Eev-00009M-Qp for linux-arm-kernel@lists.infradead.org; Fri, 31 Aug 2012 00:00:26 +0000 X-IronPort-AV: E=McAfee;i="5400,1158,6820"; a="229136540" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine02.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 30 Aug 2012 17:00:24 -0700 Received: from sboyd-linux.qualcomm.com (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 5A43C10004B6; Thu, 30 Aug 2012 17:00:24 -0700 (PDT) From: Stephen Boyd To: Will Deacon Subject: [PATCHv2] ARM: msm: Implement read_current_timer for msm timers Date: Thu, 30 Aug 2012 17:00:22 -0700 Message-Id: <1346371222-7450-1-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 1.7.12.70.g851f7e6 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.251 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-msm@vger.kernel.org, Jonathan Austin , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Setup the same timer used as the clocksource to be used as the read_current_timer implementation. This allows us to support a stable udelay implementation on MSMs where it's possible for the CPUs to scale speeds independently of one another. Signed-off-by: Stephen Boyd Acked-by: David Brown --- Changes since v1: * Updated for new function signature arch/arm/mach-msm/timer.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index ce6b008..6e3b91b 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "common.h" @@ -173,6 +174,15 @@ static notrace u32 msm_sched_clock_read(void) return msm_clocksource.read(&msm_clocksource); } +static unsigned long msm_read_current_timer(void) +{ + return msm_clocksource.read(&msm_clocksource); +} + +static struct delay_timer msm_delay_timer = { + .read_current_timer = msm_read_current_timer, +}; + static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, bool percpu) { @@ -217,6 +227,8 @@ err: if (res) pr_err("clocksource_register failed\n"); setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz); + msm_delay_timer.freq = dgt_hz; + register_current_timer_delay(&msm_delay_timer); } #ifdef CONFIG_OF