From patchwork Mon Sep 10 15:23:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 1432621 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 007DFDF28C for ; Mon, 10 Sep 2012 15:29:48 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TB5sO-0007Sk-6p; Mon, 10 Sep 2012 15:26:16 +0000 Received: from bear.ext.ti.com ([192.94.94.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TB5qF-0006O9-5K for linux-arm-kernel@lists.infradead.org; Mon, 10 Sep 2012 15:24:09 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id q8AFNvHx030965; Mon, 10 Sep 2012 10:23:57 -0500 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8AFNvRF005876; Mon, 10 Sep 2012 10:23:57 -0500 Received: from dlelxv24.itg.ti.com (172.17.1.199) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Mon, 10 Sep 2012 10:23:56 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id q8AFNv4q001983; Mon, 10 Sep 2012 10:23:57 -0500 Received: from localhost (h56-53.vpn.ti.com [172.24.56.53]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id q8AFNur01009; Mon, 10 Sep 2012 10:23:56 -0500 (CDT) From: Jon Hunter To: Tony Lindgren Subject: [PATCH V3 8/8] ARM: OMAP2+: PMU: Add QoS constraint Date: Mon, 10 Sep 2012 10:23:46 -0500 Message-ID: <1347290626-21164-9-git-send-email-jon-hunter@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1347290626-21164-1-git-send-email-jon-hunter@ti.com> References: <1347290626-21164-1-git-send-email-jon-hunter@ti.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -7.3 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.94.94.41 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Kevin Hilman , Paul Walmsley , Benoit Cousson , Ming Lei , Will Deacon , Jon Hunter , linux-omap , linux-arm X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org When CPU-idle is enabled, the MPU sub-system will transition to low power states during idle periods. If the PMU is active and the MPU sub-system transitions to a low power state, such as retention, then the PMU context will be lost and PMU events will stop. To prevent this from happening add a QoS constraint whenever PMU is active to prevent the MPU sub-system from transitioning to a low power state. By default the PMU QoS constraint is set to -1 so it will not prevent any low power states and when the PMU is enabled, it is set to 0, so that only C-state C0 is allowed. I plan to re-visit this and relax the constraint to allow some low power states, but for now I just wish to ensure PMU is working. Cc: Ming Lei Cc: Will Deacon Cc: Benoit Cousson Cc: Paul Walmsley Cc: Kevin Hilman Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/pmu.c | 49 +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 47 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c index 7fbaa3f..ca158f0 100644 --- a/arch/arm/mach-omap2/pmu.c +++ b/arch/arm/mach-omap2/pmu.c @@ -13,6 +13,7 @@ * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ +#include #include #include @@ -24,11 +25,41 @@ static char *omap2_pmu_oh_names[] = {"mpu"}; static char *omap3_pmu_oh_names[] = {"mpu", "debugss"}; static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"}; +static struct pm_qos_request pmu_pm_qos_request; static struct platform_device *omap_pmu_dev; -static struct arm_pmu_platdata omap_pmu_data; static struct cti omap4_cti[2]; /** + * omap_pmu_runtime_resume - PMU runtime resume callback + * @dev OMAP PMU device + * + * Platform specific PMU runtime resume callback for OMAP devices to + * configure the cross trigger interface for routing PMU interrupts. + * This is called by the PM runtime framework. + */ +static int omap_pmu_runtime_resume(struct device *dev) +{ + pm_qos_update_request(&pmu_pm_qos_request, 0); + + return 0; +} + +/** + * omap_pmu_runtime_suspend - PMU runtime suspend callback + * @dev OMAP PMU device + * + * Platform specific PMU runtime suspend callback for OMAP devices to + * disable the cross trigger interface interrupts. This is called by + * the PM runtime framework. + */ +static int omap_pmu_runtime_suspend(struct device *dev) +{ + pm_qos_update_request(&pmu_pm_qos_request, PM_QOS_DEFAULT_VALUE); + + return 0; +} + +/** * omap4_pmu_runtime_resume - PMU runtime resume callback * @dev OMAP PMU device * @@ -38,6 +69,8 @@ static struct cti omap4_cti[2]; */ static int omap4_pmu_runtime_resume(struct device *dev) { + pm_qos_update_request(&pmu_pm_qos_request, 0); + /* configure CTI0 for PMU IRQ routing */ cti_unlock(&omap4_cti[0]); cti_map_trigger(&omap4_cti[0], 1, 6, 2); @@ -64,6 +97,8 @@ static int omap4_pmu_runtime_suspend(struct device *dev) cti_disable(&omap4_cti[0]); cti_disable(&omap4_cti[1]); + pm_qos_update_request(&pmu_pm_qos_request, PM_QOS_DEFAULT_VALUE); + return 0; } @@ -111,6 +146,11 @@ static int __init omap4_init_cti(void) return 0; } +static struct arm_pmu_platdata omap_pmu_data = { + .runtime_resume = omap_pmu_runtime_resume, + .runtime_suspend = omap_pmu_runtime_suspend, +}; + /** * omap2_init_pmu - creates and registers PMU platform device * @oh_num: Number of OMAP HWMODs required to create PMU device @@ -183,6 +223,11 @@ static int __init omap_init_pmu(void) oh_names = omap2_pmu_oh_names; } - return omap2_init_pmu(oh_num, oh_names); + r = omap2_init_pmu(oh_num, oh_names); + if (!r) + pm_qos_add_request(&pmu_pm_qos_request, PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); + + return r; } subsys_initcall(omap_init_pmu);