From patchwork Wed Sep 12 07:14:56 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 1441341 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (unknown [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 4A3C63FC71 for ; Wed, 12 Sep 2012 07:24:03 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TBhAk-00051i-7a; Wed, 12 Sep 2012 07:15:42 +0000 Received: from kirsty.vergenet.net ([202.4.237.240]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TBhAK-0004vq-KZ for linux-arm-kernel@lists.infradead.org; Wed, 12 Sep 2012 07:15:19 +0000 Received: from ayumi.akashicho.tokyo.vergenet.net (p6117-ipbfp1901kobeminato.hyogo.ocn.ne.jp [114.172.117.117]) by kirsty.vergenet.net (Postfix) with ESMTP id A2ABC266CE0; Wed, 12 Sep 2012 17:15:11 +1000 (EST) Received: by ayumi.akashicho.tokyo.vergenet.net (Postfix, from userid 7100) id 540D0EDE60F; Wed, 12 Sep 2012 16:15:10 +0900 (JST) From: Simon Horman To: Russell King Subject: [PATCH 1/2] arm: Add ARM ERRATA 775420 workaround Date: Wed, 12 Sep 2012 16:14:56 +0900 Message-Id: <1347434097-7924-2-git-send-email-horms@verge.net.au> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1347434097-7924-1-git-send-email-horms@verge.net.au> References: <1347434097-7924-1-git-send-email-horms@verge.net.au> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -3.0 (---) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-3.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [202.4.237.240 listed in list.dnswl.org] -0.3 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Paul Mundt , Magnus Damm , linux-arm-kernel@lists.infradead.org, linux-sh@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Kouei Abe Signed-off-by: Kouei Abe Signed-off-by: Simon Horman --- arch/arm/Kconfig | 10 ++++++++++ arch/arm/kernel/entry-armv.S | 17 +++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2f88d8d..74fbdf7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419 on systems with an outer cache, the store buffer is drained explicitly. +config ARM_ERRATA_775420 + bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" + depends on CPU_V7 + help + This option enables the workaround for the 775420 Cortex-A9 (r2p2, + r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance + operation aborts with MMU exception, it might cause the processor + deadlock. This workaround puts DSB before executing ISB at the + beginning of the abort exception handler. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 0f82098..070fa62 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -989,10 +989,19 @@ __kuser_helper_end: * SP points to a minimal amount of processor-private memory, the address * of which is copied into r0 for the mode specific abort handler. */ +#ifdef CONFIG_ARM_ERRATA_775420 + .macro vector_stub, name, mode, correction=0, abort=0 +#else .macro vector_stub, name, mode, correction=0 +#endif .align 5 vector_\name: +#ifdef CONFIG_ARM_ERRATA_775420 + .if \abort + dsb + .endif +#endif .if \correction sub lr, lr, #\correction .endif @@ -1056,7 +1065,11 @@ __stubs_start: * Data abort dispatcher * Enter in ABT mode, spsr = USR CPSR, lr = USR PC */ +#ifdef CONFIG_ARM_ERRATA_775420 + vector_stub dabt, ABT_MODE, 8, 1 +#else vector_stub dabt, ABT_MODE, 8 +#endif .long __dabt_usr @ 0 (USR_26 / USR_32) .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) @@ -1079,7 +1092,11 @@ __stubs_start: * Prefetch abort dispatcher * Enter in ABT mode, spsr = USR CPSR, lr = USR PC */ +#ifdef CONFIG_ARM_ERRATA_775420 + vector_stub pabt, ABT_MODE, 4, 1 +#else vector_stub pabt, ABT_MODE, 4 +#endif .long __pabt_usr @ 0 (USR_26 / USR_32) .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)