| Message ID | 1347551658-24449-3-git-send-email-thomas.petazzoni@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 09/13/2012 10:54 AM, Thomas Petazzoni wrote: > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > Cc: Grant Likely <grant.likely@secretlab.ca> > Cc: Linus Walleij <linus.walleij@stericsson.com> > Cc: Andrew Lunn <andrew@lunn.ch> > Cc: Jason Cooper <jason@lakedaemon.net> > Cc: Gregory Clement <gregory.clement@free-electrons.com> > --- Grant is pretty much offline right now. Acked-by: Rob Herring <rob.herring@calxeda.com> > .../devicetree/bindings/gpio/gpio-mvebu.txt | 45 ++++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt > > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt > new file mode 100644 > index 0000000..595be9e > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt > @@ -0,0 +1,45 @@ > +* Marvell EBU GPIO controller > + > +Required properties: > + > +- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio" > + or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for > + Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada > + 370. "marvell,mv78200-gpio" should be used for the Discovery > + MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP > + SoCs (MV78230, MV78260, MV78460). > + > +- reg: Address and length of the register set for the device. Only one > + entry is expected, except for the "marvell,armadaxp-gpio" variant > + for which two entries are expected: one for the general registers, > + one for the per-cpu registers. > + > +- interrupts: The list of interrupts that are used for all the pins > + managed by this GPIO bank. There can be more than one interrupt > + (example: 1 interrupt per 8 pins on Armada XP, which means 4 > + interrupts per bank of 32 GPIOs). > + > +- interrupt-controller: identifies the node as an interrupt controller > + > +- #interrupt-cells: specifies the number of celles needed to encode an > + interrupt source > + > +- gpio-controller: marks the device node as a gpio controller > + > +- ngpios: number of GPIOs this controller has > + > +- #gpio-cells: Should be two. The first is the pin number. The second > + is reserved for flags, unused at the moment. > + > +Example: > + > + gpio0: gpio@d0018100 { > + compatible = "marvell,armadaxp-gpio"; > + reg = <0xd0018100 0x40>, > + <0xd0018800 0x30>; > + ngpios = <32>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + interrupts = <16>, <17>, <18>, <19>; > + }; >
Dear Rob Herring, On Thu, 13 Sep 2012 15:20:54 -0500, Rob Herring wrote: > On 09/13/2012 10:54 AM, Thomas Petazzoni wrote: > > Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> > > Cc: Grant Likely <grant.likely@secretlab.ca> > > Cc: Linus Walleij <linus.walleij@stericsson.com> > > Cc: Andrew Lunn <andrew@lunn.ch> > > Cc: Jason Cooper <jason@lakedaemon.net> > > Cc: Gregory Clement <gregory.clement@free-electrons.com> > > --- > > Grant is pretty much offline right now. Yes, I know, but MAINTAINERS does not mention an alternate maintainer for the GPIO subsystem. Who is the interim maintainer that will ultimately have to ack/nack those patches? > Acked-by: Rob Herring <rob.herring@calxeda.com> Thanks! Thomas
On 09/13/2012 03:30 PM, Thomas Petazzoni wrote: > Dear Rob Herring, > > On Thu, 13 Sep 2012 15:20:54 -0500, Rob Herring wrote: >> On 09/13/2012 10:54 AM, Thomas Petazzoni wrote: >>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> >>> Cc: Grant Likely <grant.likely@secretlab.ca> >>> Cc: Linus Walleij <linus.walleij@stericsson.com> >>> Cc: Andrew Lunn <andrew@lunn.ch> >>> Cc: Jason Cooper <jason@lakedaemon.net> >>> Cc: Gregory Clement <gregory.clement@free-electrons.com> >>> --- >> >> Grant is pretty much offline right now. > > Yes, I know, but MAINTAINERS does not mention an alternate maintainer > for the GPIO subsystem. Who is the interim maintainer that will > ultimately have to ack/nack those patches? Linus W. is. Rob
On Thu, Sep 13, 2012 at 10:34 PM, Rob Herring <robherring2@gmail.com> wrote: > On 09/13/2012 03:30 PM, Thomas Petazzoni wrote: >> Dear Rob Herring, >> >> On Thu, 13 Sep 2012 15:20:54 -0500, Rob Herring wrote: >>> On 09/13/2012 10:54 AM, Thomas Petazzoni wrote: >>>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> >>>> Cc: Grant Likely <grant.likely@secretlab.ca> >>>> Cc: Linus Walleij <linus.walleij@stericsson.com> >>>> Cc: Andrew Lunn <andrew@lunn.ch> >>>> Cc: Jason Cooper <jason@lakedaemon.net> >>>> Cc: Gregory Clement <gregory.clement@free-electrons.com> >>>> --- >>> >>> Grant is pretty much offline right now. >> >> Yes, I know, but MAINTAINERS does not mention an alternate maintainer >> for the GPIO subsystem. Who is the interim maintainer that will >> ultimately have to ack/nack those patches? > > Linus W. is. I stated Reviewed-by: on the GPIO patch, please merge it through the Marvell tree (I guess that's the plan?) Acked-by: on the rest FWIW, I'm no ARM SoC nor DT maintainer... Yours, Linus Walleij
Dear Linus Walleij, On Fri, 14 Sep 2012 15:17:09 +0200, Linus Walleij wrote: > >> Yes, I know, but MAINTAINERS does not mention an alternate maintainer > >> for the GPIO subsystem. Who is the interim maintainer that will > >> ultimately have to ack/nack those patches? > > > > Linus W. is. > > I stated Reviewed-by: on the GPIO patch, please merge it through the > Marvell tree (I guess that's the plan?) Yes, I guess it's the easiest plan (Jason ? Andrew ?). We however need Acks on the pinctrl patch series as well, since this one depends on it. Thanks a lot for your review! Thomas
On 09/13/2012 09:54 AM, Thomas Petazzoni wrote: > diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt > +- #interrupt-cells: specifies the number of celles needed to encode an > + interrupt source s/celles/cells/ What value should this property contain for this driver, and what do those cells mean? This property is missing from the example below. > + gpio0: gpio@d0018100 { > + compatible = "marvell,armadaxp-gpio"; > + reg = <0xd0018100 0x40>, > + <0xd0018800 0x30>; > + ngpios = <32>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + interrupts = <16>, <17>, <18>, <19>; > + };
On Fri, Sep 14, 2012 at 04:54:08PM +0200, Thomas Petazzoni wrote: > Dear Linus Walleij, > > On Fri, 14 Sep 2012 15:17:09 +0200, Linus Walleij wrote: > > > >> Yes, I know, but MAINTAINERS does not mention an alternate maintainer > > >> for the GPIO subsystem. Who is the interim maintainer that will > > >> ultimately have to ack/nack those patches? > > > > > > Linus W. is. > > > > I stated Reviewed-by: on the GPIO patch, please merge it through the > > Marvell tree (I guess that's the plan?) > > Yes, I guess it's the easiest plan (Jason ? Andrew ?). We however need > Acks on the pinctrl patch series as well, since this one depends on it. Yes, that's the plan. I'm currently waiting for my previous series of pull requests to get pulled before I start pulling in anything else. thx, Jason.
> +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt > @@ -0,0 +1,45 @@ > +* Marvell EBU GPIO controller > + > +Required properties: > + > +- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio" > + or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for > + Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada > + 370. "marvell,mv78200-gpio" should be used for the Discovery > + MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP > + SoCs (MV78230, MV78260, MV78460). > + > +- reg: Address and length of the register set for the device. Only one > + entry is expected, except for the "marvell,armadaxp-gpio" variant > + for which two entries are expected: one for the general registers, > + one for the per-cpu registers. > + > +- interrupts: The list of interrupts that are used for all the pins > + managed by this GPIO bank. There can be more than one interrupt > + (example: 1 interrupt per 8 pins on Armada XP, which means 4 > + interrupts per bank of 32 GPIOs). > + > +- interrupt-controller: identifies the node as an interrupt controller > + > +- #interrupt-cells: specifies the number of celles needed to encode an > + interrupt source Hi Thomas Should this be #gpio-cells? The example below does not have #interrupt-cells? Andrew > + > +- gpio-controller: marks the device node as a gpio controller > + > +- ngpios: number of GPIOs this controller has > + > +- #gpio-cells: Should be two. The first is the pin number. The second > + is reserved for flags, unused at the moment. > + > +Example: > + > + gpio0: gpio@d0018100 { > + compatible = "marvell,armadaxp-gpio"; > + reg = <0xd0018100 0x40>, > + <0xd0018800 0x30>; > + ngpios = <32>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + interrupts = <16>, <17>, <18>, <19>; > + }; > -- > 1.7.9.5 >
On 09/16/2012 09:56 AM, Andrew Lunn wrote: >> +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt >> @@ -0,0 +1,45 @@ >> +* Marvell EBU GPIO controller >> ... >> +- interrupt-controller: identifies the node as an interrupt controller >> + >> +- #interrupt-cells: specifies the number of celles needed to encode an >> + interrupt source > > Hi Thomas > > Should this be #gpio-cells? The example below does not have > #interrupt-cells? It should be both. #gpio-cells to encode pin-offset within the gpio controller and polarity, #interrupt-cells to encode irq number. Sebastian
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt new file mode 100644 index 0000000..595be9e --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt @@ -0,0 +1,45 @@ +* Marvell EBU GPIO controller + +Required properties: + +- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio" + or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for + Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada + 370. "marvell,mv78200-gpio" should be used for the Discovery + MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP + SoCs (MV78230, MV78260, MV78460). + +- reg: Address and length of the register set for the device. Only one + entry is expected, except for the "marvell,armadaxp-gpio" variant + for which two entries are expected: one for the general registers, + one for the per-cpu registers. + +- interrupts: The list of interrupts that are used for all the pins + managed by this GPIO bank. There can be more than one interrupt + (example: 1 interrupt per 8 pins on Armada XP, which means 4 + interrupts per bank of 32 GPIOs). + +- interrupt-controller: identifies the node as an interrupt controller + +- #interrupt-cells: specifies the number of celles needed to encode an + interrupt source + +- gpio-controller: marks the device node as a gpio controller + +- ngpios: number of GPIOs this controller has + +- #gpio-cells: Should be two. The first is the pin number. The second + is reserved for flags, unused at the moment. + +Example: + + gpio0: gpio@d0018100 { + compatible = "marvell,armadaxp-gpio"; + reg = <0xd0018100 0x40>, + <0xd0018800 0x30>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + interrupts = <16>, <17>, <18>, <19>; + };
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Gregory Clement <gregory.clement@free-electrons.com> --- .../devicetree/bindings/gpio/gpio-mvebu.txt | 45 ++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mvebu.txt