From patchwork Fri Sep 14 22:29:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Vaswani X-Patchwork-Id: 1461011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id C6F033FD40 for ; Fri, 14 Sep 2012 22:32:36 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TCeOL-0004Rb-QZ; Fri, 14 Sep 2012 22:29:41 +0000 Received: from wolverine01.qualcomm.com ([199.106.114.254]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TCeOH-0004RA-L5 for linux-arm-kernel@lists.infradead.org; Fri, 14 Sep 2012 22:29:39 +0000 X-IronPort-AV: E=McAfee;i="5400,1158,6835"; a="237060644" Received: from pdmz-ns-mip.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.114.10]) by wolverine01.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 14 Sep 2012 15:29:34 -0700 Received: from codeaurora.org (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 2D63310004AA; Fri, 14 Sep 2012 15:29:34 -0700 (PDT) From: Rohit Vaswani To: Marc Zyngier , David Brown , Bryan Huntsman , Daniel Walker Subject: [PATCH v2 1/2] ARM: arch timer: Set the TVAL before timer is enabled Date: Fri, 14 Sep 2012 15:29:23 -0700 Message-Id: <1347661764-3934-1-git-send-email-rvaswani@codeaurora.org> X-Mailer: git-send-email 1.7.8.3 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.254 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-arm-msm@vger.kernel.org, Rohit Vaswani , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On some hardware, the timer deasserts the interrupt when a new TVAL is written only when the enable bit is cleared. Hence explicitly disable the timer and then program the TVAL followed by enabling the timer. If this order is not followed, there are chances that you would not receive any timer interrupts. Signed-off-by: Rohit Vaswani --- arch/arm/kernel/arch_timer.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c index c04c2a6..8672a75 100644 --- a/arch/arm/kernel/arch_timer.c +++ b/arch/arm/kernel/arch_timer.c @@ -206,9 +206,10 @@ static inline void set_next_event(const int access, unsigned long evt) { unsigned long ctrl; ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL); - ctrl |= ARCH_TIMER_CTRL_ENABLE; - ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; + ctrl &= ~(ARCH_TIMER_CTRL_ENABLE | ARCH_TIMER_CTRL_IT_MASK); + arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt); + ctrl |= ARCH_TIMER_CTRL_ENABLE; arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl); }