From patchwork Thu Oct 18 10:56:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 1609821 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id A01E43FE36 for ; Thu, 18 Oct 2012 10:59:42 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TOnnb-0004j9-Fl; Thu, 18 Oct 2012 10:57:59 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TOnnN-0004gb-My for linux-arm-kernel@lists.infradead.org; Thu, 18 Oct 2012 10:57:46 +0000 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Thu, 18 Oct 2012 03:59:53 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Thu, 18 Oct 2012 03:57:34 -0700 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Thu, 18 Oct 2012 03:57:34 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.279.1; Thu, 18 Oct 2012 03:57:34 -0700 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Thu, 18 Oct 2012 03:57:34 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q9IAvSUQ007308; Thu, 18 Oct 2012 03:57:32 -0700 (PDT) From: Laxman Dewangan To: , Subject: [PATCH 1/5] ARM: tegra: Add slink controller base address Date: Thu, 18 Oct 2012 16:26:31 +0530 Message-ID: <1350557795-31487-2-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1350557795-31487-1-git-send-email-ldewangan@nvidia.com> References: <1350557795-31487-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -7.3 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, Laxman Dewangan , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add base address of all slink controller of Tegra20 and tegra30. Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/include/mach/iomap.h | 22 ++++++++++++++-------- 1 files changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index fee3a94..0f46765 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -206,17 +206,23 @@ #define TEGRA_DVC_BASE 0x7000D000 #define TEGRA_DVC_SIZE SZ_512 -#define TEGRA_SPI1_BASE 0x7000D400 -#define TEGRA_SPI1_SIZE SZ_512 +#define TEGRA_SLINK1_BASE 0x7000D400 +#define TEGRA_SLINK1_SIZE SZ_512 -#define TEGRA_SPI2_BASE 0x7000D600 -#define TEGRA_SPI2_SIZE SZ_512 +#define TEGRA_SLINK2_BASE 0x7000D600 +#define TEGRA_SLINK2_SIZE SZ_512 -#define TEGRA_SPI3_BASE 0x7000D800 -#define TEGRA_SPI3_SIZE SZ_512 +#define TEGRA_SLINK3_BASE 0x7000D800 +#define TEGRA_SLINK3_SIZE SZ_512 -#define TEGRA_SPI4_BASE 0x7000DA00 -#define TEGRA_SPI4_SIZE SZ_512 +#define TEGRA_SLINK4_BASE 0x7000DA00 +#define TEGRA_SLINK4_SIZE SZ_512 + +#define TEGRA_SLINK5_BASE 0x7000DC00 +#define TEGRA_SLINK5_SIZE SZ_512 + +#define TEGRA_SLINK6_BASE 0x7000DE00 +#define TEGRA_SLINK6_SIZE SZ_512 #define TEGRA_RTC_BASE 0x7000E000 #define TEGRA_RTC_SIZE SZ_256