From patchwork Thu Oct 18 15:53:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Mack X-Patchwork-Id: 1611761 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 39CD93FCFC for ; Thu, 18 Oct 2012 15:56:20 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TOsQM-0007kq-Fy; Thu, 18 Oct 2012 15:54:18 +0000 Received: from casper.infradead.org ([2001:770:15f::2]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TOsQI-0007kP-GD for linux-arm-kernel@merlin.infradead.org; Thu, 18 Oct 2012 15:54:14 +0000 Received: from svenfoo.org ([82.94.215.22] helo=mail.zonque.de) by casper.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TOsQE-0008Jl-Mu for linux-arm-kernel@lists.infradead.org; Thu, 18 Oct 2012 15:54:13 +0000 Received: from localhost (localhost [127.0.0.1]) by mail.zonque.de (Postfix) with ESMTP id 4855AC009B; Thu, 18 Oct 2012 17:54:02 +0200 (CEST) Received: from mail.zonque.de ([127.0.0.1]) by localhost (rambrand.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fS56WRuQf2pZ; Thu, 18 Oct 2012 17:54:02 +0200 (CEST) Received: from tamtam.taperay.com (i59F76258.versanet.de [89.247.98.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.zonque.de (Postfix) with ESMTPSA id DCB0AC00DC; Thu, 18 Oct 2012 17:54:01 +0200 (CEST) From: Daniel Mack To: rtc-linux@googlegroups.com Subject: [PATCH 3/3] RTC: omap-rtc: add DT bindings Date: Thu, 18 Oct 2012 17:53:51 +0200 Message-Id: <1350575631-15523-3-git-send-email-zonque@gmail.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1350575631-15523-1-git-send-email-zonque@gmail.com> References: <1350575631-15523-1-git-send-email-zonque@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121018_165411_085745_5499A657 X-CRM114-Status: GOOD ( 21.33 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.3.2 on casper.infradead.org summary: Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (zonque[at]gmail.com) 0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is CUSTOM_MED 0.8 SPF_NEUTRAL SPF: sender does not match SPF record (neutral) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.9 NML_ADSP_CUSTOM_MED ADSP custom_med hit, and not from a mailing list Cc: a.zummo@towertech.it, koen@dominion.thruhere.net, Daniel Mack , david-b@pacbell.net, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This adds bindings for the OMAP RTC driver. There are currently two compatible string it matches, "ti,omap-rtc" and "ti,am33xx-rtc". This is done because the AM33xx needs extra registers to be written in order to unlock the register set. Also, the OMAP_RTC_OSC_REG can be set up via DT, in particular two bits: 32KCLK_EN - Selects external clock source, namely rtc_32k_clk_rtc_32k_clk that is from the 32-kHz oscillator 32KCLK_SEL - 32-kHz clock enable post clock mux of rtc_32k_clk_rtc_32k_aux_clk and rtc_32k_clk_rtc_32k_clk Signed-off-by: Daniel Mack --- Documentation/devicetree/bindings/rtc/omap-rtc.txt | 25 +++++++ drivers/rtc/rtc-omap.c | 78 ++++++++++++++++++++++ 2 files changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/omap-rtc.txt diff --git a/Documentation/devicetree/bindings/rtc/omap-rtc.txt b/Documentation/devicetree/bindings/rtc/omap-rtc.txt new file mode 100644 index 0000000..a2abc9c --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/omap-rtc.txt @@ -0,0 +1,25 @@ +* OMAP RTC + +Required properties: +- compatible : Should be "ti,omap-rtc" or "ti,am33xx-rtc" + + +Optional properties for AM33xx +- ti,rtc-external-osc - Selects external clock source, namely + rtc_32k_clk_rtc_32k_clk that is from the + 32-kHz oscillator + +- ti,rtc-32clk-enable - 32-kHz clock enable post clock mux of + rtc_32k_clk_rtc_32k_aux_clk and + rtc_32k_clk_rtc_32k_clk + +Example for AM33xx: + +rtc@44e3e000 { + compatible = "marvell,am33xx-rtc"; + reg = <0x44e3e000 0x1000>; + interrupts = <75 76>; + ti,hwmods = "rtc"; + ti,rtc-32clk-enable; + ti,rtc-external-osc; +}; diff --git a/drivers/rtc/rtc-omap.c b/drivers/rtc/rtc-omap.c index baa876e..5529719 100644 --- a/drivers/rtc/rtc-omap.c +++ b/drivers/rtc/rtc-omap.c @@ -21,6 +21,8 @@ #include #include #include +#include +#include #include @@ -65,6 +67,9 @@ #define OMAP_RTC_COMP_MSB_REG 0x50 #define OMAP_RTC_OSC_REG 0x54 +#define AM33XX_RTC_KICK0R_REG 0x6c +#define AM33XX_RTC_KICK1R_REG 0x70 + /* OMAP_RTC_CTRL_REG bit fields: */ #define OMAP_RTC_CTRL_SPLIT (1<<7) #define OMAP_RTC_CTRL_DISABLE (1<<6) @@ -286,6 +291,76 @@ static struct rtc_class_ops omap_rtc_ops = { static int omap_rtc_alarm; static int omap_rtc_timer; +enum { + OMAP_RTC_HW_OMAP = 0, + OMAP_RTC_HW_AM33XX, +}; + +#ifdef CONFIG_OF +static const struct of_device_id of_omap_rtc_match[] = { + { + .compatible = "ti,omap-rtc", + .data = (void *) OMAP_RTC_HW_OMAP, + }, + { + .compatible = "ti,am33xx-rtc", + .data = (void *) OMAP_RTC_HW_AM33XX, + }, + { } +}; + +static int omap_rtc_probe_dt(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + int hw_type; + u32 val; + + match = of_match_device(of_omap_rtc_match, &pdev->dev); + + if (!match) + return 0; + + hw_type = (int) match->data; + + if (hw_type == OMAP_RTC_HW_AM33XX) { + /* + * From the datasheet: + * + * The kick registers (KICKnR) are used to enable and disable + * write protection on the RTC registers. Out of reset, the RTC + * registers are write-protected. To disable write protection, + * correct keys must be written to the KICKnR registers. The + * Kick0 register allows writing to unlock the kick0 data. + */ + __raw_writel(0x83e70b13, rtc_base + AM33XX_RTC_KICK0R_REG); + __raw_writel(0x95a4f1e0, rtc_base + AM33XX_RTC_KICK1R_REG); + + /* Set RTC_OSC_REG */ + val = __raw_readl(rtc_base + OMAP_RTC_OSC_REG); + if (of_get_property(np, "ti,rtc-32clk-enable", NULL)) + val |= (1 << 6); + else + val &= ~(1 << 6); + + if (of_get_property(np, "ti,rtc-external-osc", NULL)) + val |= (1 << 3); + else + val &= ~(1 << 3); + + __raw_writel(val, rtc_base + OMAP_RTC_OSC_REG); + } + + return 0; +} + +#else +static int omap_rtc_probe_dt(struct platform_device *pdev) +{ + return 0; +} +#endif + static int __init omap_rtc_probe(struct platform_device *pdev) { struct resource *res, *mem; @@ -326,6 +401,8 @@ static int __init omap_rtc_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); pm_runtime_get_sync(&pdev->dev); + omap_rtc_probe_dt(pdev); + rtc = rtc_device_register(pdev->name, &pdev->dev, &omap_rtc_ops, THIS_MODULE); if (IS_ERR(rtc)) { @@ -483,6 +560,7 @@ static struct platform_driver omap_rtc_driver = { .driver = { .name = "omap_rtc", .owner = THIS_MODULE, + .of_match_table = of_match_ptr(of_omap_rtc_match), }, };