From patchwork Fri Oct 19 22:41:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 1620211 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 68CEC3FC1A for ; Fri, 19 Oct 2012 22:44:33 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TPLHI-0005Tw-V8; Fri, 19 Oct 2012 22:42:53 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TPLGU-0005Bj-7h for linux-arm-kernel@lists.infradead.org; Fri, 19 Oct 2012 22:42:03 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id 1C0A4622E; Fri, 19 Oct 2012 16:42:40 -0600 (MDT) Received: from localhost.localdomain (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 3F35DE47A4; Fri, 19 Oct 2012 16:42:00 -0600 (MDT) From: Stephen Warren To: Stephen Warren Subject: [PATCH V3 4/5] ARM: tegra: don't include iomap.h from debug-macro.S Date: Fri, 19 Oct 2012 16:41:46 -0600 Message-Id: <1350686507-3022-4-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1350686507-3022-1-git-send-email-swarren@wwwdotorg.org> References: <1350686507-3022-1-git-send-email-swarren@wwwdotorg.org> X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Russell King - ARM Linux , Arnd Bergmann , Rob Herring , linux-tegra@vger.kernel.org, Olof Johansson , Stephen Warren , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren In order to move Tegra's debug-macro.S to a common location for single zImage, it must not rely on any machine-specific header files such as . Duplicate the few physical address definitions that debug-macro.S relies upon directly into the file. To avoid tegra_io_desc[] requiring shared knowledge of the UART mapping's virtual address, use a virtual address outside the ranges in tegra_io_desc[]. Call debug_ll_io_init() to propagate the mapping beyond the early pages tables. Signed-off-by: Stephen Warren --- v3: New patch. --- arch/arm/mach-tegra/include/mach/debug-macro.S | 24 +++++++++++++++++++----- arch/arm/mach-tegra/io.c | 1 + 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S index d4c23d6..f67fd6d 100644 --- a/arch/arm/mach-tegra/include/mach/debug-macro.S +++ b/arch/arm/mach-tegra/include/mach/debug-macro.S @@ -26,10 +26,18 @@ #include -#include "../../iomap.h" - #define UART_SHIFT 2 +/* Physical addresses */ +#define TEGRA_CLK_RESET_BASE 0x60006000 +#define TEGRA_APB_MISC_BASE 0x70000000 +#define TEGRA_UARTA_BASE 0x70006000 +#define TEGRA_UARTB_BASE 0x70006040 +#define TEGRA_UARTC_BASE 0x70006200 +#define TEGRA_UARTD_BASE 0x70006300 +#define TEGRA_UARTE_BASE 0x70006400 +#define TEGRA_PMC_BASE 0x7000e400 + #define TEGRA_CLK_RST_DEVICES_L (TEGRA_CLK_RESET_BASE + 0x04) #define TEGRA_CLK_RST_DEVICES_H (TEGRA_CLK_RESET_BASE + 0x08) #define TEGRA_CLK_RST_DEVICES_U (TEGRA_CLK_RESET_BASE + 0x0c) @@ -39,6 +47,12 @@ #define TEGRA_PMC_SCRATCH20 (TEGRA_PMC_BASE + 0xa0) #define TEGRA_APB_MISC_GP_HIDREV (TEGRA_APB_MISC_BASE + 0x804) +/* + * Must be 1MB-aligned since a 1MB mapping is used early on. + * Must not overlap with regions in mach-tegra/io.c:tegra_io_desc[]. + */ +#define UART_VIRTUAL_BASE 0xfe100000 + #define checkuart(rp, rv, lhu, bit, uart) \ /* Load address of CLK_RST register */ \ movw rp, #TEGRA_CLK_RST_DEVICES_##lhu & 0xffff ; \ @@ -139,10 +153,10 @@ 91: str \rp, [\tmp, #4] @ Store in tegra_uart_phys cmp \rp, #0 @ Valid UART address? bne 92f @ Yes, go process it - str \rp, [\tmp, #8] @ Store 0 in tegra_uart_phys + str \rp, [\tmp, #8] @ Store 0 in tegra_uart_virt b 100f @ Done -92: sub \rv, \rp, #IO_APB_PHYS @ Calculate virt address - add \rv, \rv, #IO_APB_VIRT +92: and \rv, \rp, #0xffffff @ offset within 1MB section + add \rv, \rv, #UART_VIRTUAL_BASE str \rv, [\tmp, #8] @ Store in tegra_uart_virt movw \rv, #TEGRA_APB_MISC_GP_HIDREV & 0xffff movt \rv, #TEGRA_APB_MISC_GP_HIDREV >> 16 diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c index 7d09f30..bb9c9c2 100644 --- a/arch/arm/mach-tegra/io.c +++ b/arch/arm/mach-tegra/io.c @@ -59,5 +59,6 @@ static struct map_desc tegra_io_desc[] __initdata = { void __init tegra_map_common_io(void) { + debug_ll_io_init(); iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc)); }