@@ -19,6 +19,7 @@
#define GPC_IMR1 0x008
#define GPC_PGC_CPU_PDN 0x2a0
+#define GPC_PGC_CPU_PUPSCR 0x2a4
#define IMR_NUM 4
@@ -106,6 +107,9 @@ void __init imx_gpc_init(void)
gpc_base = of_iomap(np, 0);
WARN_ON(!gpc_base);
+ /* Initialize cpu power up counters to minimize the latency */
+ writel_relaxed(0x101, gpc_base + GPC_PGC_CPU_PUPSCR);
+
/* Register GPC as the secondary interrupt controller behind GIC */
gic_arch_extn.irq_mask = imx_gpc_irq_mask;
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
The default values of cpu power up counters are unnecessarily large. Initialize them to small ones for minimizing the power up latency. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> --- arch/arm/mach-imx/gpc.c | 4 ++++ 1 file changed, 4 insertions(+)