From patchwork Wed Oct 24 05:34:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanho Park X-Patchwork-Id: 1635631 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id D4B9A3FCF7 for ; Wed, 24 Oct 2012 05:38:31 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TQte2-0001vM-GD; Wed, 24 Oct 2012 05:36:46 +0000 Received: from mailout1.samsung.com ([203.254.224.24]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TQtct-0001dM-Qm for linux-arm-kernel@lists.infradead.org; Wed, 24 Oct 2012 05:35:36 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCD00G1UU39Y6G0@mailout1.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 24 Oct 2012 14:35:24 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-89-50877e1cbd66 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id C5.B4.12699.C1E77805; Wed, 24 Oct 2012 14:35:24 +0900 (KST) Received: from localhost.localdomain ([10.90.51.45]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCD0053YU6W5670@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 24 Oct 2012 14:35:24 +0900 (KST) From: Chanho Park To: kgene.kim@samsung.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 2/5] ARM: EXYNOS: Correct combined IRQs for exynos4 Date: Wed, 24 Oct 2012 14:34:51 +0900 Message-id: <1351056894-5790-3-git-send-email-chanho61.park@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1351056894-5790-1-git-send-email-chanho61.park@samsung.com> References: <1351056894-5790-1-git-send-email-chanho61.park@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrPJMWRmVeSWpSXmKPExsVy+t9jQV2ZuvYAgz//OSw2Pb7G6sDosXlJ fQBjFJdNSmpOZllqkb5dAlfGsY2TmAo+y1bsn6rZwHhCoouRk0NCwERiz/ZnzBC2mMSFe+vZ uhi5OIQEpjNKLJt5H8pZyySx/fJPsCo2AV2JLc9fMXYxcnCICKRIXNmpAlLDLHCAUeLl6evs IDXCAm4SU/tPsIDYLAKqEvNenWUDsXkFPCQeP//ACtIrIaAgMWeSDYjJKeApcX5FFUiFEFBF 74PtLBMYeRcwMqxiFE0tSC4oTkrPNdIrTswtLs1L10vOz93ECPb2M+kdjKsaLA4xCnAwKvHw Jp5oCxBiTSwrrsw9xCjBwawkwjv5LlCINyWxsiq1KD++qDQntfgQozQHi5I4b7NHSoCQQHpi SWp2ampBahFMlomDU6qBsW+XnQz/dtl9vaWt3xYK7o1R1P74Qv6zTMOKTRvnuJzm0XJ18t3j +XMDi9baDMtN51U2u1lYhfT06gQ4zFTVfDVTe/o99fUfPdxVG5Y8X5XSItg7r2F19xFFw0oO 5i1NJQ6s06sFnQ612q84pd9ndbo83Z/JQdrNION6S8Pj9DCLFgHhA6pKLMUZiYZazEXFiQCF ExGr8gEAAA== X-Spam-Note: CRM114 invocation failed X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.24 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux@arm.linux.org.uk, sachin.kamat@linaro.org, will.deacon@arm.com, kyungmin.park@samsung.com, thomas.abraham@linaro.org, ben-linux@fluff.org, Chanho Park X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org This patch corrects combined IRQs for exynos4 series platform. The exynos4412 has four extra combined irq group and the exynos4212 has two more combined irqs than exynos4210. Each irq is mapped to IRQ_SPI(xx). Unfortunately, extra 4 combined IRQs isn't sequential. So, we need to map the irqs manually. Signed-off-by: Chanho Park Signed-off-by: Kyungmin Park --- arch/arm/mach-exynos/common.c | 50 ++++++++++++++++++++++-------- arch/arm/mach-exynos/include/mach/irqs.h | 5 ++- 2 files changed, 41 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 709245e..19a5460 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -486,16 +486,22 @@ static struct irq_chip combiner_chip = { #endif }; -static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) +static unsigned int max_combiner_nr(void) { - unsigned int max_nr; - if (soc_is_exynos5250()) - max_nr = EXYNOS5_MAX_COMBINER_NR; + return EXYNOS5_MAX_COMBINER_NR; + else if (soc_is_exynos4412()) + return EXYNOS4412_MAX_COMBINER_NR; + else if (soc_is_exynos4212()) + return EXYNOS4212_MAX_COMBINER_NR; else - max_nr = EXYNOS4_MAX_COMBINER_NR; + return EXYNOS4210_MAX_COMBINER_NR; +} - if (combiner_nr >= max_nr) +static void __init combiner_cascade_irq(unsigned int combiner_nr, + unsigned int irq) +{ + if (combiner_nr >= max_combiner_nr()) BUG(); if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0) BUG(); @@ -560,23 +566,38 @@ static struct irq_domain_ops combiner_irq_domain_ops = { .map = combiner_irq_domain_map, }; +static unsigned int exynos4x12_combiner_extra_irq(int group) +{ + switch (group) { + case 16: + return IRQ_SPI(107); + case 17: + return IRQ_SPI(108); + case 18: + return IRQ_SPI(48); + case 19: + return IRQ_SPI(42); + default: + return 0; + } +} + static void __init combiner_init(void __iomem *combiner_base, struct device_node *np) { int i, irq, irq_base; unsigned int max_nr, nr_irq; + max_nr = max_combiner_nr(); + if (np) { if (of_property_read_u32(np, "samsung,combiner-nr", &max_nr)) { - pr_warning("%s: number of combiners not specified, " + pr_info("%s: number of combiners not specified, " "setting default as %d.\n", - __func__, EXYNOS4_MAX_COMBINER_NR); - max_nr = EXYNOS4_MAX_COMBINER_NR; + __func__, max_nr); } - } else { - max_nr = soc_is_exynos5250() ? EXYNOS5_MAX_COMBINER_NR : - EXYNOS4_MAX_COMBINER_NR; } + nr_irq = max_nr * MAX_IRQ_IN_COMBINER; irq_base = irq_alloc_descs(COMBINER_IRQ(0, 0), 1, nr_irq, 0); @@ -593,7 +614,10 @@ static void __init combiner_init(void __iomem *combiner_base, } for (i = 0; i < max_nr; i++) { - irq = IRQ_SPI(i); + if (i < EXYNOS4210_MAX_COMBINER_NR || soc_is_exynos5250()) + irq = IRQ_SPI(i); + else + irq = exynos4x12_combiner_extra_irq(i); #ifdef CONFIG_OF if (np) irq = irq_of_parse_and_map(np, i); diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 35bced6..e740a6f 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h @@ -165,7 +165,10 @@ #define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1) #define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2) -#define EXYNOS4_MAX_COMBINER_NR 16 +#define EXYNOS4210_MAX_COMBINER_NR 16 +#define EXYNOS4212_MAX_COMBINER_NR 18 +#define EXYNOS4412_MAX_COMBINER_NR 20 +#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR #define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16 #define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9