From patchwork Wed Oct 24 14:25:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Lunn X-Patchwork-Id: 1638631 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id CDE60DF2AB for ; Wed, 24 Oct 2012 14:27:53 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TR1uG-0000wL-SW; Wed, 24 Oct 2012 14:26:04 +0000 Received: from londo.lunn.ch ([80.238.139.98]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TR1tr-0000tS-Q6 for linux-arm-kernel@lists.infradead.org; Wed, 24 Oct 2012 14:25:42 +0000 Received: from lunn by londo.lunn.ch with local (Exim 3.36 #1 (Debian)) id 1TR1tn-0002uq-00; Wed, 24 Oct 2012 16:25:35 +0200 From: Andrew Lunn To: Jason Cooper Subject: [PATCH 3/5] pinctrl: dove: fix iomem and pdma clock Date: Wed, 24 Oct 2012 16:25:22 +0200 Message-Id: <1351088724-11142-4-git-send-email-andrew@lunn.ch> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1351088724-11142-1-git-send-email-andrew@lunn.ch> References: <1351088724-11142-1-git-send-email-andrew@lunn.ch> X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linus.walleij@linaro.org, linux ARM , Sebastian Hesselbarth X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Sebastian Hesselbarth Since 3.7 readl/writel require register addresses to be const void* instead of unsigned int. The register addresses are converted using IOMEM() and offsets are added instead of OR'ed. Also a workaround for the pdma clock is added, that is required as there is still no DT clock provider available on Dove. Signed-off-by: Sebastian Hesselbarth --- drivers/pinctrl/pinctrl-dove.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c index ffe74b2..70befaa 100644 --- a/drivers/pinctrl/pinctrl-dove.c +++ b/drivers/pinctrl/pinctrl-dove.c @@ -22,22 +22,22 @@ #include "pinctrl-mvebu.h" -#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 -#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) +#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) +#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) #define DOVE_AU0_AC97_SEL BIT(16) -#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) +#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) #define DOVE_TWSI_ENABLE_OPTION1 BIT(7) -#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) +#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) #define DOVE_TWSI_ENABLE_OPTION2 BIT(20) #define DOVE_TWSI_ENABLE_OPTION3 BIT(21) #define DOVE_TWSI_OPTION3_GPIO BIT(22) -#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) +#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) #define DOVE_SSP_ON_AU1 BIT(0) -#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) +#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) #define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) #define DOVE_NAND_GPIO_EN BIT(0) -#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) +#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) #define DOVE_SPI_GPIO_SEL BIT(5) #define DOVE_UART1_GPIO_SEL BIT(4) @@ -587,6 +587,12 @@ static int __devinit dove_pinctrl_probe(struct platform_device *pdev) * grab clk to make sure it is ticking. */ clk = devm_clk_get(&pdev->dev, NULL); + + /* Currently there is no DT clock provider for pdma clock, + this fallback ensures pdma clock is ticking */ + if (IS_ERR(clk)) + clk = clk_get_sys("dove-pdma", NULL); + if (!IS_ERR(clk)) clk_prepare_enable(clk);