From patchwork Thu Oct 25 16:34:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Hilman X-Patchwork-Id: 1645901 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 53661DF2AB for ; Thu, 25 Oct 2012 16:36:42 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TRQO1-0008BH-3Q; Thu, 25 Oct 2012 16:34:25 +0000 Received: from mail-pb0-f49.google.com ([209.85.160.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TRQNx-0008Al-TB for linux-arm-kernel@lists.infradead.org; Thu, 25 Oct 2012 16:34:22 +0000 Received: by mail-pb0-f49.google.com with SMTP id xa7so1975586pbc.36 for ; Thu, 25 Oct 2012 09:34:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=ATHvEd2xbVQfCfGahR4//FH8qjU6ZvMwwZnwXzUTbHM=; b=B5zEzCIbihu/Th2BkGXCHFAxIEDDmv5zwofrlXWeG4gY6+k+GmWZZ8VD6YSEn2ckN6 Cchf/IV1FoyTqxksSEt34m0MYLXfLsR/tyWsZYJQMCoPbpQFq9hW7oq0T7xSZgrgYrNB 6N5k/4L6W+y/1THVihEDGR9Nvx7EivPWMRLYduZCfRoTHJTx2m/9CsyT+cXBBdEXW0In 4OOq4DyOxsjQkr+dOw3FPDKAJ5s9Qz78jr07ToJ/HeRCkeotwk0xZYitl4Yzyrdisqn4 MEl7H8zt4lYtGncezlBQDowwMpt4S5XmmMKqE8SaTuo4fDWlsJWt22oL5zfEtYWdycuE BqZw== Received: by 10.68.197.9 with SMTP id iq9mr60551977pbc.130.1351182860683; Thu, 25 Oct 2012 09:34:20 -0700 (PDT) Received: from localhost (c-24-19-7-36.hsd1.wa.comcast.net. [24.19.7.36]) by mx.google.com with ESMTPS id hc4sm11443443pbc.30.2012.10.25.09.34.19 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 25 Oct 2012 09:34:20 -0700 (PDT) From: Kevin Hilman To: Linus Walleij , Jon Hunter , linux-omap@vger.kernel.org Subject: [PATCH v3] gpio/omap: fix off-mode bug: clear debounce clock enable mask on free/reset Date: Thu, 25 Oct 2012 09:34:18 -0700 Message-Id: <1351182858-14045-1-git-send-email-khilman@deeprootsystems.com> X-Mailer: git-send-email 1.8.0 X-Gm-Message-State: ALoCoQmPqQGij6UOIb999OlMIKu+T/d5Qx2JcD0WI9IMx5Ea1Bpip5hoEol/q24mM8vaSSsBggTj X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.160.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Paul Walmsley , Santosh Shilimkar , Igor Grinberg , linux-arm-kernel@lists.infradead.org, Grazvydas Ignotas X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Kevin Hilman When a GPIO is freed or shutdown, ensure that the proper bit in dbck_enable_mask is cleared also. Otherwise, context restore on subsequent off-mode transition will restore previous debounce values from the shadow copies (bank->context.debounce*) leading to mismatch state between driver state and hardware state. This was discovered when board code was doing gpio_request_one() gpio_set_debounce() gpio_free() which was leaving the GPIO debounce settings in a confused state. If that GPIO bank is subsequently used with off-mode enabled, bogus state would be restored, leaving GPIO debounce enabled which then prevented the CORE powerdomain from transitioning. To fix, ensure that right bit in bank->dbck_enable_mask is cleared when a GPIO is freed/shutdown so debounce state doesn't persist after free/reset. If this GPIO is the last debounce-enabled GPIO in the bank, the debounce will also be cut. Special thanks to Grazvydas Ignotas for pointing out a bug in the first version that would've disabled debounce on any runtime PM transition. And, special thanks to Jon Hunter for pointing out a bug in the second version which was mistakenly clearing all debounce bits on reset instead of individual GPIOs, as well as suggesting cutting the debounce clock after all debounce bits are cleared. Tesed on 37xx/EVM board which configures GPIO debounce for the ads7846 touchscreen in its board file using the above sequence, and so was failing off-mode tests in dynamic idle. Verified that off-mode tests are passing with this patch. Reported-by: Paul Walmsley Cc: Igor Grinberg Cc: Grazvydas Ignotas Cc: Jon Hunter Signed-off-by: Kevin Hilman --- drivers/gpio/gpio-omap.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 94cbc84..ce1da19 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -539,6 +539,8 @@ static void _reset_gpio(struct gpio_bank *bank, int gpio) _set_gpio_irqenable(bank, gpio, 0); _clear_gpio_irqstatus(bank, gpio); _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); + bank->dbck_enable_mask &= ~(GPIO_BIT(bank, gpio)); + _gpio_dbck_disable(bank); } /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */