| Message ID | 1351247649-15859-1-git-send-email-josephl@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10/26/2012 04:34 AM, Joseph Lo wrote: > Add L2 cache controller binding into DT for Tegra. > diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi > + L2: cache-controller@50043000 { > + compatible = "arm,pl310-cache"; > + reg = <0x50043000 0x1000>; > + arm,data-latency = <5 5 2>; > + arm,tag-latency = <4 4 2>; > + cache-unified; > + cache-level = <2>; > + }; Do you need to specify arm,filter-ranges here? It's certainly parsed by pl310_of_setup() and used if present, although I don't think we're programming the register in the existing code, so I guess we don't need it. The L2 label above isn't necessary unless something references those nodes. Usually, that something is the cpu nodes' next-level-cache property. I don't suppose you could amend this series to also fill in Tegra's /cpus nodes in these files too? Finally, is this series going to be a dependency for any of the cpuidle or other work you're submitting? I assume it's completely independent and hence I can throw it in any old branch in any order I feel like? Thanks.
On Sat, 2012-10-27 at 01:04 +0800, Stephen Warren wrote: > On 10/26/2012 04:34 AM, Joseph Lo wrote: > > Add L2 cache controller binding into DT for Tegra. > > > diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi > > > + L2: cache-controller@50043000 { > > + compatible = "arm,pl310-cache"; > > + reg = <0x50043000 0x1000>; > > + arm,data-latency = <5 5 2>; > > + arm,tag-latency = <4 4 2>; > > + cache-unified; > > + cache-level = <2>; > > + }; > Stephen, Thanks for review. > Do you need to specify arm,filter-ranges here? It's certainly parsed by > pl310_of_setup() and used if present, although I don't think we're > programming the register in the existing code, so I guess we don't need it. > Yes, we don't need it. Because there are HW reset value for it. We don't need to configure it. > The L2 label above isn't necessary unless something references those > nodes. Usually, that something is the cpu nodes' next-level-cache > property. I don't suppose you could amend this series to also fill in > Tegra's /cpus nodes in these files too? OK. Will remove the label. > > Finally, is this series going to be a dependency for any of the cpuidle > or other work you're submitting? I assume it's completely independent > and hence I can throw it in any old branch in any order I feel like? No. We need this before the "powered-down" cpuidle support. Because the L2 init function didn't help to hook the resume API to "outer_cache_fns" interface currently. If we don't apply this before the "powered-down" cpuidle, we will lost L2 support after one successful powered-down cpuidle sequence. Thanks, Joseph
On 10/28/2012 08:28 PM, Joseph Lo wrote: > On Sat, 2012-10-27 at 01:04 +0800, Stephen Warren wrote: >> On 10/26/2012 04:34 AM, Joseph Lo wrote: >>> Add L2 cache controller binding into DT for Tegra. ... >> Finally, is this series going to be a dependency for any of the cpuidle >> or other work you're submitting? I assume it's completely independent >> and hence I can throw it in any old branch in any order I feel like? > > No. We need this before the "powered-down" cpuidle support. Because the > L2 init function didn't help to hook the resume API to "outer_cache_fns" > interface currently. If we don't apply this before the "powered-down" > cpuidle, we will lost L2 support after one successful powered-down > cpuidle sequence. OK, please do mention dependencies like this when posting the patches. Thanks.
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 6934bca..be18361 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -4,6 +4,15 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; + L2: cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <5 5 2>; + arm,tag-latency = <4 4 2>; + cache-unified; + cache-level = <2>; + }; + timer@50004600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 81f5df4..71da933 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -4,6 +4,15 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; + L2: cache-controller@50043000 { + compatible = "arm,pl310-cache"; + reg = <0x50043000 0x1000>; + arm,data-latency = <6 6 2>; + arm,tag-latency = <5 5 2>; + cache-unified; + cache-level = <2>; + }; + timer@50004600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x50040600 0x20>;
Add L2 cache controller binding into DT for Tegra. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- arch/arm/boot/dts/tegra20.dtsi | 9 +++++++++ arch/arm/boot/dts/tegra30.dtsi | 9 +++++++++ 2 files changed, 18 insertions(+), 0 deletions(-)