From patchwork Mon Oct 29 10:25:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1662761 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 8499ADFB7A for ; Mon, 29 Oct 2012 10:27:40 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TSmXQ-0001C2-6B; Mon, 29 Oct 2012 10:25:44 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TSmXL-0001BY-Bl for linux-arm-kernel@lists.infradead.org; Mon, 29 Oct 2012 10:25:41 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Mon, 29 Oct 2012 03:25:04 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Mon, 29 Oct 2012 03:25:35 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Mon, 29 Oct 2012 03:25:35 -0700 Received: from localhost.localdomain (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.279.1; Mon, 29 Oct 2012 03:25:34 -0700 From: Joseph Lo To: Stephen Warren Subject: [PATCH V2] ARM: tegra30: clocks: add AHB and APB clocks Date: Mon, 29 Oct 2012 18:25:29 +0800 Message-ID: <1351506329-32427-1-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.7.0.4 X-NVConfidentiality: public MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.35 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joseph Lo X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Adding the AHB and APB bus clock for Tegra30. Signed-off-by: Joseph Lo --- V2: * fix the round_rate func when "rate >= parent_rate" --- arch/arm/mach-tegra/common.c | 4 + arch/arm/mach-tegra/tegra30_clocks.c | 106 +++++++++++++++++++++++++++++ arch/arm/mach-tegra/tegra30_clocks.h | 1 + arch/arm/mach-tegra/tegra30_clocks_data.c | 46 +++++++++++++ 4 files changed, 157 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 0b0a5f5..177f164 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -104,6 +104,10 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { { "clk_m", NULL, 0, true }, { "pll_p", "clk_m", 408000000, true }, { "pll_p_out1", "pll_p", 9600000, true }, + { "pll_p_out4", "pll_p", 102000000, true }, + { "sclk", "pll_p_out4", 102000000, true }, + { "hclk", "sclk", 102000000, true }, + { "pclk", "hclk", 51000000, true }, { NULL, NULL, 0, 0}, }; #endif diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index e9de5df..665618a 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -792,6 +792,112 @@ struct clk_ops tegra30_twd_ops = { .recalc_rate = tegra30_twd_clk_recalc_rate, }; +/* bus clock functions */ +static int tegra30_bus_clk_is_enabled(struct clk_hw *hw) +{ + struct clk_tegra *c = to_clk_tegra(hw); + u32 val = clk_readl(c->reg); + + c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; + return c->state; +} + +static int tegra30_bus_clk_enable(struct clk_hw *hw) +{ + struct clk_tegra *c = to_clk_tegra(hw); + u32 val; + + val = clk_readl(c->reg); + val &= ~(BUS_CLK_DISABLE << c->reg_shift); + clk_writel(val, c->reg); + + return 0; +} + +static void tegra30_bus_clk_disable(struct clk_hw *hw) +{ + struct clk_tegra *c = to_clk_tegra(hw); + u32 val; + + val = clk_readl(c->reg); + val |= BUS_CLK_DISABLE << c->reg_shift; + clk_writel(val, c->reg); +} + +static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct clk_tegra *c = to_clk_tegra(hw); + u32 val = clk_readl(c->reg); + u64 rate = prate; + + c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; + c->mul = 1; + + if (c->mul != 0 && c->div != 0) { + rate *= c->mul; + rate += c->div - 1; /* round up */ + do_div(rate, c->div); + } + return rate; +} + +static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_tegra *c = to_clk_tegra(hw); + int ret = -EINVAL; + u32 val; + int i; + + val = clk_readl(c->reg); + for (i = 1; i <= 4; i++) { + if (rate == parent_rate / i) { + val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); + val |= (i - 1) << c->reg_shift; + clk_writel(val, c->reg); + c->div = i; + c->mul = 1; + ret = 0; + break; + } + } + + return ret; +} + +static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + unsigned long parent_rate = *prate; + s64 divider; + + if (rate >= parent_rate) + return parent_rate; + + divider = parent_rate; + divider += rate - 1; + do_div(divider, rate); + + if (divider < 0) + return divider; + + if (divider > 4) + divider = 4; + do_div(parent_rate, divider); + + return parent_rate; +} + +struct clk_ops tegra30_bus_ops = { + .is_enabled = tegra30_bus_clk_is_enabled, + .enable = tegra30_bus_clk_enable, + .disable = tegra30_bus_clk_disable, + .set_rate = tegra30_bus_clk_set_rate, + .round_rate = tegra30_bus_clk_round_rate, + .recalc_rate = tegra30_bus_clk_recalc_rate, +}; + /* Blink output functions */ static int tegra30_blink_clk_is_enabled(struct clk_hw *hw) { diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h index f2f88fe..7a34adb 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.h +++ b/arch/arm/mach-tegra/tegra30_clocks.h @@ -34,6 +34,7 @@ extern struct clk_ops tegra_clk_out_ops; extern struct clk_ops tegra30_super_ops; extern struct clk_ops tegra30_blink_clk_ops; extern struct clk_ops tegra30_twd_ops; +extern struct clk_ops tegra30_bus_ops; extern struct clk_ops tegra30_periph_clk_ops; extern struct clk_ops tegra30_dsib_clk_ops; extern struct clk_ops tegra_nand_clk_ops; diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c index 3d2e553..7bc8b1d 100644 --- a/arch/arm/mach-tegra/tegra30_clocks_data.c +++ b/arch/arm/mach-tegra/tegra30_clocks_data.c @@ -711,6 +711,50 @@ static struct clk tegra_clk_sclk = { .num_parents = ARRAY_SIZE(mux_sclk), }; +static const char *tegra_hclk_parent_names[] = { + "tegra_sclk", +}; + +static struct clk *tegra_hclk_parents[] = { + &tegra_clk_sclk, +}; + +static struct clk tegra_hclk; +static struct clk_tegra tegra_hclk_hw = { + .hw = { + .clk = &tegra_hclk, + }, + .flags = DIV_BUS, + .reg = 0x30, + .reg_shift = 4, + .max_rate = 378000000, + .min_rate = 12000000, +}; +DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names, + tegra_hclk_parents, &tegra_clk_sclk); + +static const char *tegra_pclk_parent_names[] = { + "tegra_hclk", +}; + +static struct clk *tegra_pclk_parents[] = { + &tegra_hclk, +}; + +static struct clk tegra_pclk; +static struct clk_tegra tegra_pclk_hw = { + .hw = { + .clk = &tegra_pclk, + }, + .flags = DIV_BUS, + .reg = 0x30, + .reg_shift = 0, + .max_rate = 167000000, + .min_rate = 12000000, +}; +DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names, + tegra_pclk_parents, &tegra_hclk); + static const char *mux_blink[] = { "clk_32k", }; @@ -1325,6 +1369,8 @@ struct clk *tegra_ptr_clks[] = { &tegra_cml1, &tegra_pciex, &tegra_clk_sclk, + &tegra_hclk, + &tegra_pclk, &tegra_clk_blink, &tegra30_clk_twd, };