From patchwork Mon Oct 29 17:19:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 1664891 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 2003FDFB7A for ; Mon, 29 Oct 2012 17:24:35 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TSt2r-0000F2-7n; Mon, 29 Oct 2012 17:22:37 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TSt2D-00008m-Of for linux-arm-kernel@lists.infradead.org; Mon, 29 Oct 2012 17:21:59 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Mon, 29 Oct 2012 10:21:16 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 29 Oct 2012 10:09:14 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 29 Oct 2012 10:09:14 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.279.1; Mon, 29 Oct 2012 10:21:45 -0700 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Mon, 29 Oct 2012 10:21:46 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q9THLY5A004571; Mon, 29 Oct 2012 10:21:43 -0700 (PDT) From: Laxman Dewangan To: , Subject: [PATCH V2 2/4] ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt Date: Mon, 29 Oct 2012 22:49:38 +0530 Message-ID: <1351531180-1652-3-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1351531180-1652-1-git-send-email-ldewangan@nvidia.com> References: <1351531180-1652-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.35 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, Laxman Dewangan , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add OF_DEV_AUXDATA for slink driver for Tegra20 and Tegra30 board dt files. Set the parent clock of slink controller to PLLP and configure clock to 100MHz. Signed-off-by: Laxman Dewangan --- Changes from V1: - Revert the changes in clock table to get the driver name. arch/arm/mach-tegra/board-dt-tegra20.c | 8 ++++++++ arch/arm/mach-tegra/board-dt-tegra30.c | 12 ++++++++++++ arch/arm/mach-tegra/include/mach/iomap.h | 22 ++++++++++++++-------- 3 files changed, 34 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 2053f74..3fdcb45 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -90,6 +90,10 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { &tegra_ehci3_pdata), OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL), OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK1_BASE, "spi_tegra.0", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK2_BASE, "spi_tegra.1", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK3_BASE, "spi_tegra.2", NULL), + OF_DEV_AUXDATA("nvidia,tegra20-slink", TEGRA_SLINK4_BASE, "spi_tegra.3", NULL), {} }; @@ -109,6 +113,10 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "sdmmc1", "pll_p", 48000000, false}, { "sdmmc3", "pll_p", 48000000, false}, { "sdmmc4", "pll_p", 48000000, false}, + { "sbc1", "pll_p", 100000000, false }, + { "sbc2", "pll_p", 100000000, false }, + { "sbc3", "pll_p", 100000000, false }, + { "sbc4", "pll_p", 100000000, false }, { NULL, NULL, 0, 0}, }; diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 9e6f79a..ec7c35d 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -52,6 +52,12 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL), OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL), OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK1_BASE, "spi_tegra.0", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK2_BASE, "spi_tegra.1", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK3_BASE, "spi_tegra.2", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK4_BASE, "spi_tegra.3", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK5_BASE, "spi_tegra.4", NULL), + OF_DEV_AUXDATA("nvidia,tegra30-slink", TEGRA_SLINK6_BASE, "spi_tegra.5", NULL), {} }; @@ -71,6 +77,12 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "sdmmc1", "pll_p", 48000000, false}, { "sdmmc3", "pll_p", 48000000, false}, { "sdmmc4", "pll_p", 48000000, false}, + { "sbc1", "pll_p", 100000000, false}, + { "sbc2", "pll_p", 100000000, false}, + { "sbc3", "pll_p", 100000000, false}, + { "sbc4", "pll_p", 100000000, false}, + { "sbc5", "pll_p", 100000000, false}, + { "sbc6", "pll_p", 100000000, false}, { NULL, NULL, 0, 0}, }; diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h index fee3a94..0f46765 100644 --- a/arch/arm/mach-tegra/include/mach/iomap.h +++ b/arch/arm/mach-tegra/include/mach/iomap.h @@ -206,17 +206,23 @@ #define TEGRA_DVC_BASE 0x7000D000 #define TEGRA_DVC_SIZE SZ_512 -#define TEGRA_SPI1_BASE 0x7000D400 -#define TEGRA_SPI1_SIZE SZ_512 +#define TEGRA_SLINK1_BASE 0x7000D400 +#define TEGRA_SLINK1_SIZE SZ_512 -#define TEGRA_SPI2_BASE 0x7000D600 -#define TEGRA_SPI2_SIZE SZ_512 +#define TEGRA_SLINK2_BASE 0x7000D600 +#define TEGRA_SLINK2_SIZE SZ_512 -#define TEGRA_SPI3_BASE 0x7000D800 -#define TEGRA_SPI3_SIZE SZ_512 +#define TEGRA_SLINK3_BASE 0x7000D800 +#define TEGRA_SLINK3_SIZE SZ_512 -#define TEGRA_SPI4_BASE 0x7000DA00 -#define TEGRA_SPI4_SIZE SZ_512 +#define TEGRA_SLINK4_BASE 0x7000DA00 +#define TEGRA_SLINK4_SIZE SZ_512 + +#define TEGRA_SLINK5_BASE 0x7000DC00 +#define TEGRA_SLINK5_SIZE SZ_512 + +#define TEGRA_SLINK6_BASE 0x7000DE00 +#define TEGRA_SLINK6_SIZE SZ_512 #define TEGRA_RTC_BASE 0x7000E000 #define TEGRA_RTC_SIZE SZ_256