From patchwork Tue Nov 6 13:15:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1704421 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id B911EDF230 for ; Tue, 6 Nov 2012 13:19:25 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TVj1g-0001PV-91; Tue, 06 Nov 2012 13:17:08 +0000 Received: from eu1sys200aog111.obsmtp.com ([207.126.144.131]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1TVj0h-0000mG-GY for linux-arm-kernel@lists.infradead.org; Tue, 06 Nov 2012 13:16:09 +0000 Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob111.postini.com ([207.126.147.11]) with SMTP ID DSNKUJkNk4BUj0fkut59gkeC+9nSfjApoPuR@postini.com; Tue, 06 Nov 2012 13:16:07 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 7856C44; Tue, 6 Nov 2012 13:15:28 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 4BFA04A; Tue, 6 Nov 2012 08:33:54 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id C2D76A8072; Tue, 6 Nov 2012 14:15:56 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 6 Nov 2012 14:16:01 +0100 From: Linus Walleij To: Subject: [PATCH 8/9] ARM: ux500: add STM pin configuration Date: Tue, 6 Nov 2012 14:15:59 +0100 Message-ID: <1352207759-8062-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121106_081608_312401_74253806 X-CRM114-Status: GOOD ( 13.09 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.131 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Anmar Oueja , Jean-Nicolas Graux , Linus Walleij X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Jean-Nicolas Graux This patch add the new stm pinctrl states definitions for the Ux500 MOP500 series. Signed-off-by: Jean-Nicolas Graux Reviewed-by: Philippe Langlais Signed-off-by: Linus Walleij --- arch/arm/mach-ux500/board-mop500-pins.c | 185 ++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c index 05102ad..f9ef2f4 100644 --- a/arch/arm/mach-ux500/board-mop500-pins.c +++ b/arch/arm/mach-ux500/board-mop500-pins.c @@ -96,6 +96,10 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE| #define DB8500_PIN_SLEEP(pin, conf, dev) \ PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \ pin, conf) +#define DB8500_MUX_STATE(group, func, dev, state) \ + PIN_MAP_MUX_GROUP(dev, state, "pinctrl-db8500", group, func) +#define DB8500_PIN_STATE(pin, conf, dev, state) \ + PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf) /* Pin control settings */ static struct pinctrl_map __initdata mop500_family_pinmap[] = { @@ -366,6 +370,187 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = { DB8500_PIN_SLEEP("GPIO166_A22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O2 */ DB8500_PIN_SLEEP("GPIO167_B24", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O1 */ DB8500_PIN_SLEEP("GPIO168_C22", slpm_out_lo_pdis, "nmk-ske-keypad"), /* O0 */ + + /* STM APE pins states */ + DB8500_MUX_STATE("stmape_c_1", "stmape", + "stm", "ape_mipi34"), + DB8500_PIN_STATE("GPIO70_G5", in_nopull, + "stm", "ape_mipi34"), /* clk */ + DB8500_PIN_STATE("GPIO71_G4", in_nopull, + "stm", "ape_mipi34"), /* dat3 */ + DB8500_PIN_STATE("GPIO72_H4", in_nopull, + "stm", "ape_mipi34"), /* dat2 */ + DB8500_PIN_STATE("GPIO73_H3", in_nopull, + "stm", "ape_mipi34"), /* dat1 */ + DB8500_PIN_STATE("GPIO74_J3", in_nopull, + "stm", "ape_mipi34"), /* dat0 */ + + DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, + "stm", "ape_mipi34_sleep"), /* clk */ + DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, + "stm", "ape_mipi34_sleep"), /* dat3 */ + DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, + "stm", "ape_mipi34_sleep"), /* dat2 */ + DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, + "stm", "ape_mipi34_sleep"), /* dat1 */ + DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, + "stm", "ape_mipi34_sleep"), /* dat0 */ + + DB8500_MUX_STATE("stmape_oc1_1", "stmape", + "stm", "ape_microsd"), + DB8500_PIN_STATE("GPIO23_AA4", in_nopull, + "stm", "ape_microsd"), /* clk */ + DB8500_PIN_STATE("GPIO25_Y4", in_nopull, + "stm", "ape_microsd"), /* dat0 */ + DB8500_PIN_STATE("GPIO26_Y2", in_nopull, + "stm", "ape_microsd"), /* dat1 */ + DB8500_PIN_STATE("GPIO27_AA2", in_nopull, + "stm", "ape_microsd"), /* dat2 */ + DB8500_PIN_STATE("GPIO28_AA1", in_nopull, + "stm", "ape_microsd"), /* dat3 */ + + DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis, + "stm", "ape_microsd_sleep"), /* clk */ + DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis, + "stm", "ape_microsd_sleep"), /* dat0 */ + DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis, + "stm", "ape_microsd_sleep"), /* dat1 */ + DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis, + "stm", "ape_microsd_sleep"), /* dat2 */ + DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis, + "stm", "ape_microsd_sleep"), /* dat3 */ + + /* STM Modem pins states */ + DB8500_MUX_STATE("stmmod_oc3_2", "stmmod", + "stm", "mod_mipi34"), + DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", + "stm", "mod_mipi34"), + DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", + "stm", "mod_mipi34"), + DB8500_PIN_STATE("GPIO70_G5", in_nopull, + "stm", "mod_mipi34"), /* clk */ + DB8500_PIN_STATE("GPIO71_G4", in_nopull, + "stm", "mod_mipi34"), /* dat3 */ + DB8500_PIN_STATE("GPIO72_H4", in_nopull, + "stm", "mod_mipi34"), /* dat2 */ + DB8500_PIN_STATE("GPIO73_H3", in_nopull, + "stm", "mod_mipi34"), /* dat1 */ + DB8500_PIN_STATE("GPIO74_J3", in_nopull, + "stm", "mod_mipi34"), /* dat0 */ + DB8500_PIN_STATE("GPIO75_H2", in_pu, + "stm", "mod_mipi34"), /* uartmod rx */ + DB8500_PIN_STATE("GPIO76_J2", out_lo, + "stm", "mod_mipi34"), /* uartmod tx */ + + DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, + "stm", "mod_mipi34_sleep"), /* clk */ + DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, + "stm", "mod_mipi34_sleep"), /* dat3 */ + DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, + "stm", "mod_mipi34_sleep"), /* dat2 */ + DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, + "stm", "mod_mipi34_sleep"), /* dat1 */ + DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, + "stm", "mod_mipi34_sleep"), /* dat0 */ + DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, + "stm", "mod_mipi34_sleep"), /* uartmod rx */ + DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, + "stm", "mod_mipi34_sleep"), /* uartmod tx */ + + DB8500_MUX_STATE("stmmod_b_1", "stmmod", + "stm", "mod_microsd"), + DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", + "stm", "mod_microsd"), + DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", + "stm", "mod_microsd"), + DB8500_PIN_STATE("GPIO23_AA4", in_nopull, + "stm", "mod_microsd"), /* clk */ + DB8500_PIN_STATE("GPIO25_Y4", in_nopull, + "stm", "mod_microsd"), /* dat0 */ + DB8500_PIN_STATE("GPIO26_Y2", in_nopull, + "stm", "mod_microsd"), /* dat1 */ + DB8500_PIN_STATE("GPIO27_AA2", in_nopull, + "stm", "mod_microsd"), /* dat2 */ + DB8500_PIN_STATE("GPIO28_AA1", in_nopull, + "stm", "mod_microsd"), /* dat3 */ + DB8500_PIN_STATE("GPIO75_H2", in_pu, + "stm", "mod_microsd"), /* uartmod rx */ + DB8500_PIN_STATE("GPIO76_J2", out_lo, + "stm", "mod_microsd"), /* uartmod tx */ + + DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis, + "stm", "mod_microsd_sleep"), /* clk */ + DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis, + "stm", "mod_microsd_sleep"), /* dat0 */ + DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis, + "stm", "mod_microsd_sleep"), /* dat1 */ + DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis, + "stm", "mod_microsd_sleep"), /* dat2 */ + DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis, + "stm", "mod_microsd_sleep"), /* dat3 */ + DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, + "stm", "mod_microsd_sleep"), /* uartmod rx */ + DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, + "stm", "mod_microsd_sleep"), /* uartmod tx */ + + /* STM dual Modem/APE pins state */ + DB8500_MUX_STATE("stmmod_oc3_2", "stmmod", + "stm", "mod_mipi34_ape_mipi60"), + DB8500_MUX_STATE("stmape_c_2", "stmape", + "stm", "mod_mipi34_ape_mipi60"), + DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod", + "stm", "mod_mipi34_ape_mipi60"), + DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod", + "stm", "mod_mipi34_ape_mipi60"), + DB8500_PIN_STATE("GPIO70_G5", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* clk */ + DB8500_PIN_STATE("GPIO71_G4", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* dat3 */ + DB8500_PIN_STATE("GPIO72_H4", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* dat2 */ + DB8500_PIN_STATE("GPIO73_H3", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* dat1 */ + DB8500_PIN_STATE("GPIO74_J3", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* dat0 */ + DB8500_PIN_STATE("GPIO75_H2", in_pu, + "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */ + DB8500_PIN_STATE("GPIO76_J2", out_lo, + "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */ + DB8500_PIN_STATE("GPIO155_C19", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* clk */ + DB8500_PIN_STATE("GPIO156_C17", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* dat3 */ + DB8500_PIN_STATE("GPIO157_A18", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* dat2 */ + DB8500_PIN_STATE("GPIO158_C18", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* dat1 */ + DB8500_PIN_STATE("GPIO159_B19", in_nopull, + "stm", "mod_mipi34_ape_mipi60"), /* dat0 */ + + DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */ + DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */ + DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */ + DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */ + DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */ + DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */ + DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */ + DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */ + DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */ + DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */ + DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */ + DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis, + "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */ }; /*