From patchwork Wed Nov 7 10:46:58 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 1709761 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 753D93FC8F for ; Wed, 7 Nov 2012 10:43:52 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TW352-0004zs-Ap; Wed, 07 Nov 2012 10:41:56 +0000 Received: from mailout2.samsung.com ([203.254.224.25]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TW34z-0004zO-6E for linux-arm-kernel@lists.infradead.org; Wed, 07 Nov 2012 10:41:54 +0000 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MD4001C55PO6530@mailout2.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 07 Nov 2012 19:41:50 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 49.89.12699.EEA3A905; Wed, 07 Nov 2012 19:41:50 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-f4-509a3aee79cc Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 29.89.12699.EEA3A905; Wed, 07 Nov 2012 19:41:50 +0900 (KST) Received: from localhost.localdomain ([107.108.73.92]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MD4006SP5N7OJ20@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Wed, 07 Nov 2012 19:41:50 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com Subject: [PATCH 1/3] ARM: EXYNOS5: Setup legacy i2c controller interrupts on SMDK5250 Date: Wed, 07 Nov 2012 16:16:58 +0530 Message-id: <1352285220-31544-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.6.6.1 In-reply-to: <1352285220-31544-1-git-send-email-a.kesavan@samsung.com> References: <1352285220-31544-1-git-send-email-a.kesavan@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNLMWRmVeSWpSXmKPExsWyRsSkSved1awAg0cz1C02Pb7G6sDosXlJ fQBjFJdNSmpOZllqkb5dAlfGskvvWAvOi1Zc2neMpYHxp2AXIyeHhICJxK+7rxghbDGJC/fW s4HYQgJLGSXWP46DqVn7u4EJIj6dUeLlbh0Iez2TxISXaSA2m4CexIJ/X5lBbBEBe4kVJ04C 2RwcwgLhEs07pUHCLAKqEh0Xr4Ot4hVwlXiw6y8rxHgFidMf1rKD2JwCbhJ3Z04AaxUCqtn+ gQOiVUDi2+RDLCBhCQFZiU0HgCq4gMwDbBIdq6dCjZGUOLjiBssERqEFjAyrGEVTC5ILipPS c430ihNzi0vz0vWS83M3MQJD7PS/Z9I7GFc1WBxiFOBgVOLhtUidGSDEmlhWXJl7iFGCg1lJ hHe50awAId6UxMqq1KL8+KLSnNTiQ4w+QJdMZJYSTc4Hhn9eSbyhsYm5qbGppZGRmakpDmEl cd5mj5QAIYH0xJLU7NTUgtQimHFMHJxSDYw9mzfNixY/L7fUVG15NvOLjere8rNNZ/n9ifLm OtpRnRqmOefcFfem90dnCTM7Juy9nVDIy7tdMDv14FGj+Pl3pI991pCoTBC0T37hp3c/jL/p nuEV6zbLolT11tYZmev1opd7OQlHz4yY+r6lL7g7WSApTdnEMOt9VtFH2+4/jAwHZniXKLEU ZyQaajEXFScCANl+x1heAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrNLMWRmVeSWpSXmKPExsVy+t9jQd13VrMCDA41yVtsenyN1YHRY/OS +gDGqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zByg qUoKZYk5pUChgMTiYiV9O0wTQkPcdC1gGiN0fUOC4HqMDNBAwhrGjGWX3rEWnBetuLTvGEsD 40/BLkZODgkBE4m1vxuYIGwxiQv31rOB2EIC0xklXu7WgbDXM0lMeJkGYrMJ6Eks+PeVGcQW EbCXWHHiJJDNwSEsEC7RvFMaJMwioCrRcfE6I4jNK+Aq8WDXX1aI8QoSpz+sZQexOQXcJO7O nADWKgRUs/0DxwRGngWMDKsYRVMLkguKk9JzjfSKE3OLS/PS9ZLzczcxgkP4mfQOxlUNFocY BTgYlXh4LVJnBgixJpYVV+YeYpTgYFYS4V1uNCtAiDclsbIqtSg/vqg0J7X4EKMP0FETmaVE k/OB8ZVXEm9obGJuamxqaWJhYmaJQ1hJnLfZIyVASCA9sSQ1OzW1ILUIZhwTB6dUA2Nw382j N77s/cnt8X3vpC1GDKvSnCpefnaUF8oIyBNxvlRYfCBC+6x1y1cH318CO5Q+fz+zj+ta15ST YbvS195cuFWucI/yA92lUiUlU9a47WRkt1/3ddOyl2cfKP8qeNp37fWRJVu4J/7uXZ2WUd17 wmAGa0uS0ub4xKt/vyWfeKmg9cVtqbuVEktxRqKhFnNRcSIAaWmBSo4CAAA= X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121107_054153_544564_632527A4 X-CRM114-Status: GOOD ( 13.07 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.25 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org On Exynos5 we have a new high-speed i2c controller. The interrupt sources for the legacy and new controller are muxed and are controlled via the SYSCON I2C_CFG register. At reset the interrupt source is configured for the high-speed controller, to continue using the old i2c controller we need to modify the I2C_CFG register. Signed-off-by: Abhilash Kesavan --- arch/arm/mach-exynos/include/mach/regs-pmu.h | 2 ++ arch/arm/mach-exynos/mach-exynos5-dt.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index d4e392b..684625a 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -15,6 +15,7 @@ #include #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) +#define S5P_SYSREG(x) (S3C_VA_SYS + (x)) #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) @@ -230,6 +231,7 @@ /* For EXYNOS5 */ +#define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234) #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) #define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index ed37273..7e9baf7 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include +#include #include #include @@ -97,6 +99,28 @@ static void __init exynos5250_dt_map_io(void) static void __init exynos5250_dt_machine_init(void) { + struct device_node *i2c_np; + const char *i2c_compat = "samsung,s3c2440-i2c"; + unsigned int tmp; + + /* + * Exynos5's legacy i2c controller and new high speed i2c + * controller have muxed interrupt sources. By default the + * interrupts for 4-channel HS-I2C controller are enabled. + * If node for first four channels of legacy i2c controller + * are available then re-configure the interrupts via the + * system register. + */ + for_each_compatible_node(i2c_np, NULL, i2c_compat) { + if (of_device_is_available(i2c_np)) { + if (of_alias_get_id(i2c_np, "i2c") < 4) { + tmp = readl(EXYNOS5_SYS_I2C_CFG); + writel(tmp & ~(0x1 << of_alias_get_id(i2c_np, "i2c")), + EXYNOS5_SYS_I2C_CFG); + } + } + } + of_platform_populate(NULL, of_default_bus_match_table, exynos5250_auxdata_lookup, NULL); }