From patchwork Wed Nov 7 15:19:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 1711221 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id C4F933FC8F for ; Wed, 7 Nov 2012 15:23:49 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TW7RW-0001sC-HH; Wed, 07 Nov 2012 15:21:26 +0000 Received: from mail-pa0-f49.google.com ([209.85.220.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TW7QL-0001IN-I8 for linux-arm-kernel@lists.infradead.org; Wed, 07 Nov 2012 15:20:14 +0000 Received: by mail-pa0-f49.google.com with SMTP id bi5so1146388pad.36 for ; Wed, 07 Nov 2012 07:20:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=HI6ag1yPkxSx6+MBK9V+WJnPn73uIhOdWvJJS1CAdZc=; b=WDs4b1+xJq95/4AOtgFl7NhKXuWnF9SNSIZtTYc+BmVFAOZe+kiVGlm6ySbtGuiLLj /2wkd256DYBBu2LXV27AehCEi6oW3HQGmCDtnJBdjdJNzaIlo7yKfkhaMyKcgof1LRXt NFGoCPSV/40QptS/zYxmSA+wWbKsO8oS6WvRoHQ2Fl9T3tTB1VohslKPxFvYNEBNKAyK 1jpRTGoe6u892ARNIvp1tNi2mNNG3qlaTMV+I81X7cYuOmjonxqJTTQdnzBt+351/czV fA31wo6t5PwKBkJT9EWiUlb6dRWuzcIt55mg3tkyEQR9DQ+cZfNzY6Nlv1FU3/WkekMD SHbA== Received: by 10.68.137.228 with SMTP id ql4mr8115723pbb.125.1352301613311; Wed, 07 Nov 2012 07:20:13 -0800 (PST) Received: from localhost.localdomain ([174.139.116.75]) by mx.google.com with ESMTPS id uh10sm9534245pbc.35.2012.11.07.07.20.09 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 07 Nov 2012 07:20:12 -0800 (PST) From: Haojian Zhuang To: linus.walleij@linaro.org, tony@atomide.com, swarren@wwwdotorg.org, linux-arm-kernel@lists.infradead.org, arnd@arndb.de Subject: [PATCH v4 5/9] document: devicetree: bind pinconf with pin-single Date: Wed, 7 Nov 2012 23:19:38 +0800 Message-Id: <1352301582-12244-6-git-send-email-haojian.zhuang@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com> References: <1352301582-12244-1-git-send-email-haojian.zhuang@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121107_102014_120709_B709639F X-CRM114-Status: GOOD ( 16.46 ) X-Spam-Score: -2.7 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.7 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.49 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (haojian.zhuang[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add comments with pinconf & gpio range in the document of pinctrl-single. Signed-off-by: Haojian Zhuang --- .../devicetree/bindings/pinctrl/pinctrl-single.txt | 67 +++++++++++++++++++- 1 file changed, 66 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index 2c81e45..0b8705f 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -1,7 +1,9 @@ One-register-per-pin type device tree based pinctrl driver Required properties: -- compatible : "pinctrl-single" +- compatible : "pinctrl-single" or "pinconf-single". + "pinctrl-single" means that pinconf isn't supported. + "pinconf-single" means that generic pinconf is supported. - reg : offset and length of the register set for the mux registers @@ -14,9 +16,33 @@ Optional properties: - pinctrl-single,function-off : function off mode for disabled state if available and same for all registers; if not specified, disabling of pin functions is ignored + - pinctrl-single,bit-per-mux : boolean to indicate that one register controls more than one pin +- pinctrl-single,power-source-mask : mask of setting power source in + the pinmux register + +- pinctrl-single,power-source : value of setting power source field + in the pinmux register + +- pinctrl-single,bias-mask : mask of setting bias value in the pinmux + register + +- pinctrl-single,bias-disable : value of disabling bias in the pinmux + register + +- pinctrl-single,bias-pull-down : value of setting bias pull down in + the pinmux register + +- pinctrl-single,bias-pull-up : value of setting bias pull up in the + pinmux register + +- pinctrl-single,bias : value of setting bias in the pinmux register + +- pinctrl-single,input-schmitt-mask : mask of setting input schmitt + in the pinmux register + This driver assumes that there is only one register for each pin (unless the pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. @@ -42,6 +68,25 @@ Where 0xdc is the offset from the pinctrl register base address for the device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to be used when applying this change to the register. + +Optional sub-node: In case some pins could be configured as GPIO in the pinmux +register. If both GPIO nubmer and pin base of those pins are in ascending order, +those pins could be defined as a GPIO range. The sub-node should be defined in +.dtsi files of those silicons. + +Required properties in sub-node: +- reg : offset and length of the GPIO range sub-node. + +- pinctrl-single,gpio : array of GPIO base number in the range and the GPIO + function in the pinmux register. + + range0: { + /* GPIO0 ~ GPIO54 */ + reg = <0xd401e0dc 55>; + pinctrl-single,gpio = <0 0>; + }; + + Example: /* SoC common file */ @@ -76,6 +121,26 @@ control_devconf0: pinmux@48002274 { pinctrl-single,function-mask = <0x5F>; }; +/* third controller instance for pins in gpio domain */ +pmx_gpio: pinmux@d401e000 { + compatible = "pinctrl-single"; + reg = <0xd401e000 0x0330>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + + range0: range@d401e0dc { + /* GPIO0 ~ GPIO54 */ + reg = <0xd401e0dc 0xdc>; + /* gpio base & gpio func */ + pinctrl-single,gpio = <0 0>; + }; +}; + + /* board specific .dts file */ &pmx_core {