From patchwork Wed Nov 7 18:43:02 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 1712131 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id AD8573FCAE for ; Wed, 7 Nov 2012 18:45:23 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWAb9-0004Zh-Ll; Wed, 07 Nov 2012 18:43:36 +0000 Received: from devils.ext.ti.com ([198.47.26.153]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TWAai-0004TD-Jw for linux-arm-kernel@lists.infradead.org; Wed, 07 Nov 2012 18:43:09 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id qA7Ih8Tu017467; Wed, 7 Nov 2012 12:43:08 -0600 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA7Ih8v6030161; Wed, 7 Nov 2012 12:43:08 -0600 Received: from dlelxv24.itg.ti.com (172.17.1.199) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Wed, 7 Nov 2012 12:43:07 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id qA7Ih7MT001429; Wed, 7 Nov 2012 12:43:07 -0600 Received: from localhost (ula0741266.am.dhcp.ti.com [192.157.144.139]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id qA7Ih7w28334; Wed, 7 Nov 2012 12:43:07 -0600 (CST) From: Jon Hunter To: Paul Walmsley Subject: [PATCH 3/3] ARM: OMAP4460: Workaround ABE DPLL failing to turn-on Date: Wed, 7 Nov 2012 12:43:02 -0600 Message-ID: <1352313782-21602-4-git-send-email-jon-hunter@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1352313782-21602-1-git-send-email-jon-hunter@ti.com> References: <1352313782-21602-1-git-send-email-jon-hunter@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121107_134308_838031_1182C25A X-CRM114-Status: GOOD ( 18.07 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.153 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-omap , Jon Hunter , linux-arm X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org With the latest mainline u-boot bootloader (v2012.10), timers (5-8) in the ABE power domain are failing to turn-on. The timers never come out of the disabled state when setting the module-mode field to enable. The problem was exposed when u-boot was updated to NOT configure and lock the ABE DPLL on start-up. If the ABE DPLL is configured and locked by u-boot the problem does not occur. However, if the ABE DPLL is in the idle low-power bypass state and we attempt to enable a timer in the ABE power domain, it remains stuck in the disabled state. It appears to be a problem the timer interface clock as this comes from the ABE DPLL. If we place the ABE DPLL in the MN-bypass state and not the idle low-power state, then this problem is not seen. This problem only appears to occur on OMAP4460 and not OMAP4430. Workaround this problem by locking the ABE DPLL for OMAP4460 in the kernel on boot. By locking the ABE DPLL, when clocks from the ABE DPLL are not being requested the DPLL will transition into a low-power stop mode. Signed-off-by: Jon Hunter --- arch/arm/mach-omap2/clock44xx_data.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 8a9cbad..1844661 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -46,6 +46,14 @@ #define OMAP4430_MODULEMODE_HWCTRL 0 #define OMAP4430_MODULEMODE_SWCTRL 1 +/* + * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section + * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK + * must be set to 196.608 MHz" and hence, the DPLL locked frequency is + * half of this value. + */ +#define OMAP4_DPLL_ABE_DEFFREQ 98304000 + /* Root clocks */ static struct clk extalt_clkin_ck = { @@ -3354,6 +3362,7 @@ int __init omap4xxx_clk_init(void) { struct omap_clk *c; u32 cpu_clkflg; + int rc; if (cpu_is_omap443x()) { cpu_mask = RATE_IN_4430; @@ -3400,5 +3409,18 @@ int __init omap4xxx_clk_init(void) */ clk_enable_init_clocks(); + /* + * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power + * state when turning the ABE clock domain. Workaround this by + * locking the ABE DPLL on boot. + */ + if (cpu_is_omap446x()) { + rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck); + if (!rc) + rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ); + if (rc) + pr_err("%s: failed to configure ABE DPLL!\n", __func__); + } + return 0; }