From patchwork Thu Nov 8 08:32:13 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 1714441 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 01645DF230 for ; Thu, 8 Nov 2012 08:31:08 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWNUC-0003qc-B0; Thu, 08 Nov 2012 08:29:16 +0000 Received: from mailout1.samsung.com ([203.254.224.24]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWNU4-0003nx-Ln for linux-arm-kernel@lists.infradead.org; Thu, 08 Nov 2012 08:29:11 +0000 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MD5007JKU8IEYS0@mailout1.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 08 Nov 2012 17:29:06 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 9D.12.01231.15D6B905; Thu, 08 Nov 2012 17:29:05 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-fe-509b6d515478 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 6C.12.01231.15D6B905; Thu, 08 Nov 2012 17:29:05 +0900 (KST) Received: from vivekkumarg-linuxpc.sisodomain.com ([107.108.73.134]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MD500LC6U3Q9I50@mmp2.samsung.com> for linux-arm-kernel@lists.infradead.org; Thu, 08 Nov 2012 17:29:05 +0900 (KST) From: Vivek Gautam To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org Subject: [PATCH v2] ARM: Exynos5250: Enabling dwc3-exynos driver Date: Thu, 08 Nov 2012 14:02:13 +0530 Message-id: <1352363533-14970-2-git-send-email-gautam.vivek@samsung.com> X-Mailer: git-send-email 1.7.6.5 In-reply-to: <1352363533-14970-1-git-send-email-gautam.vivek@samsung.com> References: <1352363533-14970-1-git-send-email-gautam.vivek@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsWyRsSkSjcwd3aAwayfZhabHl9jdWD02Lyk PoAxissmJTUnsyy1SN8ugSvjzeNjzAV31Ssae2+wNzBOU+hi5OSQEDCR+LxtLjuELSZx4d56 ti5GLg4hgaWMEt/+zGaGKbp7/iMzRGI6o0TP+pksEM4eJonDk2+DVbEJ6Eo0vd3FCGKLCBRJ HFx9HqyIWeAgo8TfKzPAEsICDhKrJ/1iBbFZBFQljrc2s4DYvAIeEq8mb4JapyDx5vYzMJtT wFNi3dE3TCC2EFDNy4PrmCB6BSS+TT4E1MsBVC8rsekA2HUSAmfYJO5/P88CMUdS4uCKGywT GIUXMDKsYhRNLUguKE5KzzXUK07MLS7NS9dLzs/dxAgMw9P/nkntYFzZYHGIUYCDUYmHV0Ny doAQa2JZcWXuIUYJDmYlEd5lzkAh3pTEyqrUovz4otKc1OJDjD5Al0xklhJNzgfGSF5JvKGx ibmpsamlkZGZqSkOYSVx3maPlAAhgfTEktTs1NSC1CKYcUwcnFINjGf/xPxtjpKVe85ra8z6 qu1gxWXlpMJTs6ZeU03+JefGudHXq3dhwtzHLeyqC1p2ChxjDWu89t6mJPFlYdCHw0vlWCfr CxU7nc+wU0/2zgzttz3YmlVnOjfQU3DRms0fl+eY+dRufacfybHz94yzl/g3HbR5pKeSlXsq a+KqfY4dKxdztzg+VWIpzkg01GIuKk4EAJT4JFBwAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42I5/e+xoG5g7uwAg/Mb1Sw2Pb7G6sDosXlJ fQBjVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7Q VCWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYQ1jxpvHx5gL7qpXNPbeYG9g nKbQxcjJISFgInH3/EdmCFtM4sK99WxdjFwcQgLTGSV61s9kgXD2MEkcnnwbrIpNQFei6e0u RhBbRKBI4uDq82BFzAIHGSX+XpkBlhAWcJBYPekXK4jNIqAqcby1mQXE5hXwkHg1eRPUOgWJ N7efgdmcAp4S646+YQKxhYBqXh5cxzSBkXcBI8MqRtHUguSC4qT0XEO94sTc4tK8dL3k/NxN jOAgfya1g3Flg8UhRgEORiUeXg3J2QFCrIllxZW5hxglOJiVRHiXOQOFeFMSK6tSi/Lji0pz UosPMfoAXTWRWUo0OR8YgXkl8YbGJuamxqaWJhYmZpY4hJXEeZs9UgKEBNITS1KzU1MLUotg xjFxcEo1MJ7WFr3uHPT3oLWn/Qnj57MPrZJd/N/6dNKEYCOWr19tN9SYuU95xPzmzmeWK/sn RQioMrnPjrtZoqq9Z7kowxPWVIUp5hbreV5u6kuxb597SWfPFQ7LpncLzWQq2ETMvrWtsVA1 jUnyE3bnn7lw6q4XCt7tB/fLLXhlvLRUR6dNa6vi5opPV5RYijMSDbWYi4oTAZym0NefAgAA X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121108_032909_426443_D773EAAA X-CRM114-Status: GOOD ( 15.16 ) X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.24 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: yulgon.kim@samsung.com, kgene.kim@samsung.com, p.paneri@samsung.com, linux-usb@vger.kernel.org, tomasz.figa@gmail.com, balbi@ti.com, av.tikhomirov@samsung.com, thomas.abraham@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Adding DWC3 device tree node for Exynos5250 along with the device address and clock support needed for the controller. Signed-off-by: Vivek Gautam --- .../devicetree/bindings/usb/exynos-usb.txt | 14 +++++++++++ arch/arm/boot/dts/exynos5250.dtsi | 6 +++++ arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/clock-exynos5.c | 24 ++++++++++++++++++++ arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 2 + 6 files changed, 48 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/exynos-usb.txt b/Documentation/devicetree/bindings/usb/exynos-usb.txt index 5ff3def1..a7e3eaa 100644 --- a/Documentation/devicetree/bindings/usb/exynos-usb.txt +++ b/Documentation/devicetree/bindings/usb/exynos-usb.txt @@ -38,3 +38,17 @@ Example: reg = <0x12120000 0x100>; interrupts = <0 71 0>; }; + +DWC3 +Required properties: + - compatible: should be "samsung,exynos-dwc3" for USB 3.0 DWC3 controller. + - reg: physical base address of the controller and length of memory mapped + region. + - interrupts: interrupt number to the cpu. + +Example: + usb@12000000 { + compatible = "samsung,exynos-dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index f18abe0..d349636 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -68,6 +68,12 @@ interrupts = <0 96 0>; }; + usb@12000000 { + compatible = "samsung,exynos-dwc3"; + reg = <0x12000000 0x10000>; + interrupts = <0 72 0>; + }; + rtc { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index bb3b09a..588814a 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT select ARM_AMBA select SOC_EXYNOS5250 select USE_OF + select USB_ARCH_HAS_XHCI help Machine support for Samsung EXYNOS5 machine with device tree enabled. Select this if a fdt blob is available for the EXYNOS5 SoC based board. diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index a88e0d9..ee094ee 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -740,6 +740,11 @@ static struct clk exynos5_init_clocks_off[] = { .enable = exynos5_clk_ip_fsys_ctrl , .ctrlbit = (1 << 18), }, { + .name = "usbdrd30", + .parent = &exynos5_clk_aclk_200.clk, + .enable = exynos5_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 19), + }, { .name = "usbotg", .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), @@ -1004,6 +1009,16 @@ struct clksrc_sources exynos5_clkset_group = { .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list), }; +struct clk *exynos5_clkset_usbdrd30_list[] = { + [0] = &exynos5_clk_mout_mpll.clk, + [1] = &exynos5_clk_mout_cpll.clk, +}; + +struct clksrc_sources exynos5_clkset_usbdrd30 = { + .sources = exynos5_clkset_usbdrd30_list, + .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list), +}; + /* Possible clock sources for aclk_266_gscl_sub Mux */ static struct clk *clk_src_gscl_266_list[] = { [0] = &clk_ext_xtal_mux, @@ -1288,6 +1303,15 @@ static struct clksrc_clk exynos5_clksrcs[] = { .parent = &exynos5_clk_mout_cpll.clk, }, .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 }, + }, { + .clk = { + .name = "sclk_usbdrd30", + .enable = exynos5_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 28), + }, + .sources = &exynos5_clkset_usbdrd30, + .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 }, + .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 }, }, }; diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 471ffaf..064ca1c 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -197,6 +197,7 @@ #define EXYNOS4_PA_EHCI 0x12580000 #define EXYNOS4_PA_OHCI 0x12590000 #define EXYNOS4_PA_HSPHY 0x125B0000 +#define EXYNOS5_PA_DRD 0x12000000 #define EXYNOS5_PA_EHCI 0x12110000 #define EXYNOS5_PA_OHCI 0x12120000 #define EXYNOS4_PA_MFC 0x13400000 diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index c03f3dd..3032222 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -90,6 +90,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { "s5p-ehci", NULL), OF_DEV_AUXDATA("samsung,exynos-ohci", EXYNOS5_PA_OHCI, "exynos-ohci", NULL), + OF_DEV_AUXDATA("samsung,exynos-dwc3", EXYNOS5_PA_DRD, + "exynos-dwc3", NULL), {}, };