From patchwork Fri Nov 9 12:14:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 1720221 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id AC48BDF264 for ; Fri, 9 Nov 2012 12:11:01 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWnON-00083M-M6; Fri, 09 Nov 2012 12:08:59 +0000 Received: from mailout2.samsung.com ([203.254.224.25]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TWnOJ-000832-0f for linux-arm-kernel@lists.infradead.org; Fri, 09 Nov 2012 12:08:56 +0000 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MD700J4MZ2MPN00@mailout2.samsung.com> for linux-arm-kernel@lists.infradead.org; Fri, 09 Nov 2012 21:08:50 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id CB.DB.01231.152FC905; Fri, 09 Nov 2012 21:08:50 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-08-509cf251a81f Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 9B.DB.01231.152FC905; Fri, 09 Nov 2012 21:08:49 +0900 (KST) Received: from localhost.localdomain ([107.108.73.92]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MD7006K4Z0T2O80@mmp1.samsung.com> for linux-arm-kernel@lists.infradead.org; Fri, 09 Nov 2012 21:08:49 +0900 (KST) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com Subject: [PATCH] ARM: EXYNOS5: Add arm down clock support Date: Fri, 09 Nov 2012 17:44:14 +0530 Message-id: <1352463254-28423-1-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 1.6.6.1 DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrBLMWRmVeSWpSXmKPExsWyRsSkSjfo05wAg9MnGS02Pb7G6sDosXlJ fQBjFJdNSmpOZllqkb5dAlfG9HtdTAX/FCqa3u1ka2Bslu5i5OSQEDCRWDV1MguELSZx4d56 ti5GLg4hgaWMEh8n3maHKdr0ZhULRGIRo8TbvT+hqtYzScz/sR6snU1AT2LBv6/MILaIgL3E ihMnwWxhAUuJzRM/s4HYLAKqEtN/dIPFeQVcJd6fXcoGsUFB4vSHtewQNQIS3yYfAprJARSX ldh0gBlkl4TACjaJyzuPMkHUS0ocXHGDZQKjwAJGhlWMoqkFyQXFSem5hnrFibnFpXnpesn5 uZsYgcFz+t8zqR2MKxssDjEKcDAq8fAmPpgdIMSaWFZcmXuIUYKDWUmE9+T7OQFCvCmJlVWp RfnxRaU5qcWHGH2ALpnILCWanA8M7LySeENjE3NTY1NLIyMzU1McwkrivM0eKQFCAumJJanZ qakFqUUw45g4OKUaGBX1l6xVXMJZ4jc/sWb/zIRTXXrc++4uDpD0enkg0eXexqTClFfTDzD2 z8tcHRT7ajrPHp06u4byouvz2r7NP+QbtfpVRt3Ok8+Px8sv5z/CPeWj0J3JTjKta44bL9j1 v+B1jtzRkOC7wTJJNXLNl8v3qfuoXrspIjJB7+Dj27M13+Vdq1yxzE+JpTgj0VCLuag4EQBc kAChSwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOLMWRmVeSWpSXmKPExsVy+t9jAd3AT3MCDM6sNbPY9PgaqwOjx+Yl 9QGMUQ2MNhmpiSmpRQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlA U5UUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGdPvdTEV/FOoaHq3k62B sVm6i5GTQ0LARGLTm1UsELaYxIV769m6GLk4hAQWMUq83fsTylnPJDH/x3qwKjYBPYkF/74y g9giAvYSK06cBLOFBSwlNk/8zAZiswioSkz/0Q0W5xVwlXh/dikbxAYFidMf1rJPYORawMiw ilE0tSC5oDgpPddQrzgxt7g0L10vOT93EyM4NJ9J7WBc2WBxiFGAg1GJhzfxwewAIdbEsuLK 3EOMEhzMSiK8J9/PCRDiTUmsrEotyo8vKs1JLT7E6AO0fSKzlGhyPjBu8kriDY1NzE2NTS1N LEzMLHEIK4nzNnukBAgJpCeWpGanphakFsGMY+LglGpg5ItKiClceNhh2yKnWSvMNv+fHxMc miA1P7DO3G7OLa4Hldv4JVjmSonOTczv1eqTcROK33rV4ZFSs1SMourbGbq/ewOnfZDeUcm3 tSrQ+8xPASara3UGX0szn68+uOnHqYMeBnyLpjw8zbDp2+7pwb5Tv2+1OfXiI+/3Dp+bW27b ZtQ5ZZhcVmIpzkg01GIuKk4EAHLtcCR6AgAA X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121109_070855_375319_76A4FAA4 X-CRM114-Status: GOOD ( 13.80 ) X-Spam-Score: -7.6 (-------) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-7.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [203.254.224.25 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In idle state down clocking the arm cores can result in power savings. Program the power control registers to achieve this and save these registers across a suspend/resume cycle. Signed-off-by: Abhilash Kesavan --- arch/arm/mach-exynos/clock-exynos5.c | 2 + arch/arm/mach-exynos/cpuidle.c | 36 ++++++++++++++++++++++++ arch/arm/mach-exynos/include/mach/regs-clock.h | 19 ++++++++++++ 3 files changed, 57 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index a88e0d9..9bb6567 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -80,6 +80,8 @@ static struct sleep_save exynos5_clock_save[] = { SAVE_ITEM(EXYNOS5_VPLL_CON0), SAVE_ITEM(EXYNOS5_VPLL_CON1), SAVE_ITEM(EXYNOS5_VPLL_CON2), + SAVE_ITEM(EXYNOS5_PWR_CTRL1), + SAVE_ITEM(EXYNOS5_PWR_CTRL2), }; #endif diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index cff0595..4ddda91 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include @@ -156,12 +157,47 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev, return exynos4_enter_core0_aftr(dev, drv, new_index); } +static void __init exynos5_core_down_clk(void) +{ + unsigned int tmp; + + /* + * Enable arm clock down (in idle) and set arm divider + * ratios in WFI/WFE state. + */ + tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \ + PWR_CTRL1_CORE1_DOWN_RATIO | \ + PWR_CTRL1_DIV2_DOWN_EN | \ + PWR_CTRL1_DIV1_DOWN_EN | \ + PWR_CTRL1_USE_CORE1_WFE | \ + PWR_CTRL1_USE_CORE0_WFE | \ + PWR_CTRL1_USE_CORE1_WFI | \ + PWR_CTRL1_USE_CORE0_WFI; + __raw_writel(tmp, EXYNOS5_PWR_CTRL1); + + /* + * Enable arm clock up (on exiting idle). Set arm divider + * ratios when not in idle along with the standby duration + * ratios. + */ + tmp = PWR_CTRL2_DIV2_UP_EN | \ + PWR_CTRL2_DIV1_UP_EN | \ + PWR_CTRL2_DUR_STANDBY2_VAL | \ + PWR_CTRL2_DUR_STANDBY1_VAL | \ + PWR_CTRL2_CORE2_UP_RATIO | \ + PWR_CTRL2_CORE1_UP_RATIO; + __raw_writel(tmp, EXYNOS5_PWR_CTRL2); +} + static int __init exynos4_init_cpuidle(void) { int i, max_cpuidle_state, cpu_id; struct cpuidle_device *device; struct cpuidle_driver *drv = &exynos4_idle_driver; + if (soc_is_exynos5250()) + exynos5_core_down_clk(); + /* Setup cpuidle driver */ drv->state_count = (sizeof(exynos4_cpuidle_set) / sizeof(struct cpuidle_state)); diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 8c9b38c..d36ad76 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -267,6 +267,9 @@ #define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) #define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) +#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020) +#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024) + #define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) #define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) @@ -344,6 +347,22 @@ #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) +#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) +#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) +#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) +#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) +#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) +#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) +#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) +#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) + +#define PWR_CTRL2_DIV2_UP_EN (1 << 25) +#define PWR_CTRL2_DIV1_UP_EN (1 << 24) +#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) +#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) +#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) +#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) + /* Compatibility defines and inclusion */ #include