From patchwork Fri Nov 16 18:55:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 1756951 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 4F08BDF288 for ; Fri, 16 Nov 2012 18:57:05 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TZR4c-00053m-HF; Fri, 16 Nov 2012 18:55:30 +0000 Received: from avon.wwwdotorg.org ([2001:470:1f0f:bd7::2]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TZR4Y-00052f-Fh for linux-arm-kernel@lists.infradead.org; Fri, 16 Nov 2012 18:55:27 +0000 Received: from severn.wwwdotorg.org (unknown [192.168.65.5]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPS id CA1BA6234; Fri, 16 Nov 2012 11:56:43 -0700 (MST) Received: from swarren-lx1.nvidia.com (localhost [127.0.0.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by severn.wwwdotorg.org (Postfix) with ESMTPSA id 88B7CE40EF; Fri, 16 Nov 2012 11:55:22 -0700 (MST) From: Stephen Warren To: Stephen Warren Subject: [PATCH] ARM: tegra: seaboard: enable internal LCD Date: Fri, 16 Nov 2012 11:55:14 -0700 Message-Id: <1353092114-18410-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 1.7.10.4 X-NVConfidentiality: public X-Virus-Scanned: clamav-milter 0.96.5 at avon.wwwdotorg.org X-Virus-Status: Clean X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121116_135526_769699_7613E81E X-CRM114-Status: GOOD ( 11.36 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: linux-tegra@vger.kernel.org, Stephen Warren , Alex Courbot , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Stephen Warren Enable host1x and add the rgb (LCD) output. Also add the power sequence that controls the backlight and panel. The sequence strictly follows the order and timings of the panel specification. Currently the backlight device controls both backlight and panel, this needs to be fixed once the panel framework supports power sequences. Based on (cut/paste) work for Ventana by Alexandre Courbot. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra20-seaboard.dts | 127 +++++++++++++++++++++++++++++++- 1 file changed, 126 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index eafeca6..a999430 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -10,6 +10,16 @@ reg = <0x00000000 0x40000000>; }; + host1x { + dc@54200000 { + rgb { + status = "okay"; + nvidia,ddc-i2c-bus = <&lcd_ddc>; + backlight = <&backlight>; + }; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -351,7 +361,7 @@ #size-cells = <0>; }; - i2c@1 { + lcd_ddc: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -600,6 +610,101 @@ }; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 255>; + default-brightness-level = <12>; + + /* resources used by the power sequences */ + pwms = <&pwm 2 5000000>; + pwm-names = "backlight"; + power-supply = <&vdd_bl_reg>; + panel-supply = <&vdd_panel_reg>; + + power-sequences { + power-on { + /* + * Panel power and LVDS enable. + * TODO: move into the panel device as soon as + * panel framework supports power sequences. + */ + step0 { + type = "regulator"; + id = "panel"; + enable; + }; + step1 { + /* LVDS_SHTDN* */ + type = "gpio"; + gpio = <&gpio 10 0>; /* GPIO PC6 */ + value = <1>; + }; + step2 { + type = "delay"; + delay = <200000>; + }; + /* Backlight sequence. This belongs here. */ + step3 { + type = "regulator"; + id = "power"; + enable; + }; + step4 { + type = "delay"; + delay = <10000>; + }; + step5 { + type = "pwm"; + id = "backlight"; + enable; + }; + step6 { + /* LCD_BL_EN */ + type = "gpio"; + gpio = <&gpio 28 0>; /* GPIO PD4 */ + value = <1>; + }; + }; + + power-off { + step0 { + type = "gpio"; + gpio = <&gpio 28 0>; + value = <0>; + }; + step1 { + type = "pwm"; + id = "backlight"; + disable; + }; + step2 { + type = "delay"; + delay = <10000>; + }; + step3 { + type = "regulator"; + id = "power"; + disable; + }; + /* This also belongs to the panel sequence */ + step4 { + type = "delay"; + delay = <200000>; + }; + step5 { + type = "gpio"; + gpio = <&gpio 10 0>; + value = <0>; + }; + step6 { + type = "regulator"; + id = "panel"; + disable; + }; + }; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -632,6 +737,26 @@ gpio = <&pmic 1 0>; enable-active-high; }; + + vdd_panel_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vdd_pnl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 22 0>; /* gpio PC6 */ + enable-active-high; + }; + + vdd_bl_reg: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vdd_bl"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpio 176 0>; /* gpio PW0 */ + enable-active-high; + }; }; sound {