From patchwork Wed Nov 21 07:37:45 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1778731 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 69678DF288 for ; Wed, 21 Nov 2012 07:40:12 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tb4tY-0006x2-1A; Wed, 21 Nov 2012 07:38:52 +0000 Received: from eu1sys200aog119.obsmtp.com ([207.126.144.147]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tb4tU-0006vF-61 for linux-arm-kernel@lists.infradead.org; Wed, 21 Nov 2012 07:38:48 +0000 Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob119.postini.com ([207.126.147.11]) with SMTP ID DSNKUKyE+hBDL0wqbLk1Sxm//ZmK749KPfJu@postini.com; Wed, 21 Nov 2012 07:38:47 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 5394647; Wed, 21 Nov 2012 07:37:14 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 892EE58; Wed, 21 Nov 2012 02:44:15 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id B76DCA8088; Wed, 21 Nov 2012 08:37:46 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 21 Nov 2012 08:37:49 +0100 From: Linus Walleij To: , , Shiraz Hashim , Viresh Kumar Subject: [PATCH] gpiolib: fix bug and clarify OF use of ranges Date: Wed, 21 Nov 2012 08:37:45 +0100 Message-ID: <1353483465-25961-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121121_023848_476252_65896497 X-CRM114-Status: GOOD ( 13.26 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.147 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Anmar Oueja , Grant Likely , Linus Walleij , Stephen Warren X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Linus Walleij In commit c905165f5946f56dca195871641bd4e488eca24a "gpiolib: let gpiochip_add_pin_range() specify offset" I forgot to update the OF use of the function gpiochip_add_pin_range(). It turns out that this reveal a weakness in the OF range mappings: ranges cannot currently be sparse. So put in a comment so we can fix this later. Signed-off-by: Linus Walleij Reviewed-by: Viresh Kumar --- drivers/gpio/gpiolib-of.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c index a40cd84..d542a14 100644 --- a/drivers/gpio/gpiolib-of.c +++ b/drivers/gpio/gpiolib-of.c @@ -238,8 +238,20 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip) if (!pctldev) break; + /* + * This assumes that the n GPIO pins are consecutive in the + * GPIO number space, and that the pins are also consecutive + * in their local number space. Currently it is not possible + * to add different ranges for one and the same GPIO chip, + * as the code assumes that we have one consecutive range + * on both, mapping 1-to-1. + * + * TODO: make the OF bindings handle multiple sparse ranges + * on the same GPIO chip. + */ ret = gpiochip_add_pin_range(chip, pinctrl_dev_get_name(pctldev), + 0, /* offset in gpiochip */ pinspec.args[0], pinspec.args[1]);