From patchwork Wed Nov 21 07:50:43 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1778781 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 584513FC23 for ; Wed, 21 Nov 2012 07:52:56 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tb55S-0001Kh-BG; Wed, 21 Nov 2012 07:51:10 +0000 Received: from eu1sys200aog105.obsmtp.com ([207.126.144.119]) by merlin.infradead.org with smtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tb55N-0001IQ-HC for linux-arm-kernel@lists.infradead.org; Wed, 21 Nov 2012 07:51:06 +0000 Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob105.postini.com ([207.126.147.11]) with SMTP ID DSNKUKyH3a3Txo104dTQbPhIGFobZs4BxqUs@postini.com; Wed, 21 Nov 2012 07:51:05 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 1F89193; Wed, 21 Nov 2012 07:42:36 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id A375810AC; Wed, 21 Nov 2012 07:50:48 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id CF89A24C07D; Wed, 21 Nov 2012 08:50:43 +0100 (CET) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 21 Nov 2012 08:50:47 +0100 From: Linus Walleij To: , , Shiraz Hashim , Viresh Kumar Subject: [PATCH] gpiolib: rename pin range arguments Date: Wed, 21 Nov 2012 08:50:43 +0100 Message-ID: <1353484243-6115-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121121_025105_912700_D93741CC X-CRM114-Status: GOOD ( 16.23 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.126.144.119 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Anmar Oueja , Grant Likely , Linus Walleij , Stephen Warren X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Linus Walleij To be crystal clear on what the arguments mean in this funtion dealing with both GPIO and PIN ranges with confusing naming, we now have gpio_offset and pin_offset and we are on the clear that these are offsets into the specific GPIO and pin controller respectively. The GPIO chip itself will of course keep track of the base offset into the global GPIO number space. Signed-off-by: Linus Walleij Reviewed-by: Viresh Kumar Reviewed-by: Stephen Warren --- drivers/gpio/gpiolib.c | 19 ++++++++++--------- include/asm-generic/gpio.h | 4 ++-- include/linux/gpio.h | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 317ff04..26e27c1 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1191,13 +1191,13 @@ EXPORT_SYMBOL_GPL(gpiochip_find); * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping * @chip: the gpiochip to add the range for * @pinctrl_name: the dev_name() of the pin controller to map to - * @offset: the start offset in the current gpio_chip number space - * @pin_base: the start offset in the pin controller number space + * @gpio_offset: the start offset in the current gpio_chip number space + * @pin_offset: the start offset in the pin controller number space * @npins: the number of pins from the offset of each pin space (GPIO and * pin controller) to accumulate in this range */ int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, - unsigned int offset, unsigned int pin_base, + unsigned int gpio_offset, unsigned int pin_offset, unsigned int npins) { struct gpio_pin_range *pin_range; @@ -1210,11 +1210,11 @@ int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, } /* Use local offset as range ID */ - pin_range->range.id = offset; + pin_range->range.id = gpio_offset; pin_range->range.gc = chip; pin_range->range.name = chip->label; - pin_range->range.base = chip->base + offset; - pin_range->range.pin_base = pin_base; + pin_range->range.base = chip->base + gpio_offset; + pin_range->range.pin_base = pin_offset; pin_range->range.npins = npins; pin_range->pctldev = pinctrl_find_and_add_gpio_range(pinctl_name, &pin_range->range); @@ -1224,9 +1224,10 @@ int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, kfree(pin_range); return PTR_ERR(pin_range->pctldev); } - pr_debug("%s: GPIO chip: created GPIO range %d->%d ==> PIN %d->%d\n", - chip->label, offset, offset + npins - 1, - pin_base, pin_base + npins - 1); + pr_debug("GPIO chip %s: created GPIO range %d->%d ==> %s PIN %d->%d\n", + chip->label, gpio_offset, gpio_offset + npins - 1, + pinctl_name, + pin_offset, pin_offset + npins - 1); list_add_tail(&pin_range->node, &chip->pin_ranges); diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index ec58fdb..9fd3093 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -283,7 +283,7 @@ struct gpio_pin_range { }; int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, - unsigned int offset, unsigned int pin_base, + unsigned int gpio_offset, unsigned int pin_offset, unsigned int npins); void gpiochip_remove_pin_ranges(struct gpio_chip *chip); @@ -291,7 +291,7 @@ void gpiochip_remove_pin_ranges(struct gpio_chip *chip); static inline int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, - unsigned int offset, unsigned int pin_base, + unsigned int gpio_offset, unsigned int pin_offset, unsigned int npins) { return 0; diff --git a/include/linux/gpio.h b/include/linux/gpio.h index 99861c6..bfe6656 100644 --- a/include/linux/gpio.h +++ b/include/linux/gpio.h @@ -233,7 +233,7 @@ static inline int irq_to_gpio(unsigned irq) static inline int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name, - unsigned int offset, unsigned int pin_base, + unsigned int gpio_offset, unsigned int pin_offset, unsigned int npins) { WARN_ON(1);