From patchwork Thu Nov 29 19:47:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 1822351 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id AAAACDF23A for ; Thu, 29 Nov 2012 19:51:10 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TeA5D-0002FE-CX; Thu, 29 Nov 2012 19:47:39 +0000 Received: from mail-qa0-f49.google.com ([209.85.216.49]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TeA59-0002Ef-Kw for linux-arm-kernel@lists.infradead.org; Thu, 29 Nov 2012 19:47:36 +0000 Received: by mail-qa0-f49.google.com with SMTP id hg5so635827qab.15 for ; Thu, 29 Nov 2012 11:47:34 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=VaeNyXFcAqo9Q6K4PLbvkXkszVQ/8k/ncswW77cPS5Y=; b=gXRrcfG2hqdnEFoxDg+8I5izNVz2NBeEe/Ltow35NvVkd6RcE38Rptdy4uxFjnWdsN 2AvOvkiBeEDretQo8nrxfGI1XDvahW1GerxjOeP4IxO8fT2/c2l2btueFIAH5gJAY/jC VT7LyQATG9QXLXEhvReysK8f7p4c8UkbVkI/AHN/dFz4rwzDAZAHPE6gEo5vDdZBnp5Q t2WEY8fRXGUG5EVhkB3Gr4/cnbPIR/Be91JLyjJ0E6BPurBrGPuCQD++V6KZ6dMsvfJ5 TRb6qrlSxfQxch38IonvX99eJUOuDFu9L8sRoX41I8NG5weE1K3ewj3BX0yYsJDr9BIv nxRw== Received: by 10.224.45.6 with SMTP id c6mr27520496qaf.54.1354218454256; Thu, 29 Nov 2012 11:47:34 -0800 (PST) Received: from ubuntu.columbia.edu (chazy.cs.columbia.edu. [128.59.22.176]) by mx.google.com with ESMTPS id i9sm1404464qak.3.2012.11.29.11.47.33 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 29 Nov 2012 11:47:33 -0800 (PST) From: Christoffer Dall To: linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: Factor out cpuid implementor and part number Date: Thu, 29 Nov 2012 14:47:21 -0500 Message-Id: <1354218441-24866-1-git-send-email-c.dall@virtualopensystems.com> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmbx3xyEGaOVTaHeFkHoxst+SeZen3g3biVkmvZZWfNMqpx9v4CjyPuZRjrUDVopR6iQFFf X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121129_144735_849346_7F9990F4 X-CRM114-Status: GOOD ( 15.16 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.216.49 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Christoffer Dall , will.deacon@arm.com X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Decoding the implementor and part number of the CPU id in the CPU ID register is needed by KVM, so we factor it out to share the code. Reviewed-by: Will Deacon Signed-off-by: Christoffer Dall --- Applies to Will Deacon's perf/updates branch arch/arm/include/asm/cputype.h | 26 ++++++++++++++++++++++++++ arch/arm/kernel/perf_event_cpu.c | 31 ++++++++++++++++--------------- 2 files changed, 42 insertions(+), 15 deletions(-) diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index cb47d28..306fb2c 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -51,6 +51,22 @@ extern unsigned int processor_id; #define read_cpuid_ext(reg) 0 #endif +#define IMPLEMENTOR_ARM 0x41 +#define IMPLEMENTOR_INTEL 0x69 + +#define PART_NUMBER_ARM1136 0xB360 +#define PART_NUMBER_ARM1156 0xB560 +#define PART_NUMBER_ARM1176 0xB760 +#define PART_NUMBER_ARM11MPCORE 0xB020 +#define PART_NUMBER_CORTEX_A8 0xC080 +#define PART_NUMBER_CORTEX_A9 0xC090 +#define PART_NUMBER_CORTEX_A5 0xC050 +#define PART_NUMBER_CORTEX_A15 0xC0F0 +#define PART_NUMBER_CORTEX_A7 0xC070 + +#define PART_NUMBER_XSCALE1 0x1 +#define PART_NUMBER_XSCALE2 0x2 + /* * The CPU ID never changes at run time, so we might as well tell the * compiler that it's constant. Use this function to read the CPU ID @@ -61,6 +77,16 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } +static inline unsigned int __attribute_const__ read_cpuid_implementor(void) +{ + return (read_cpuid_id() & 0xFF000000) >> 24; +} + +static inline unsigned int __attribute_const__ read_cpuid_part_number(void) +{ + return (read_cpuid_id() & 0xFFF0); +} + static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) { return read_cpuid(CPUID_CACHETYPE); diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 9a4f630..fb817e1 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -202,47 +202,48 @@ static int __devinit probe_current_pmu(struct arm_pmu *pmu) { int cpu = get_cpu(); unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number = read_cpuid_part_number(); int ret = -ENODEV; pr_info("probing PMU on CPU %d\n", cpu); /* ARM Ltd CPUs. */ - if (0x41 == implementor) { + if (implementor == IMPLEMENTOR_ARM) { switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ + case PART_NUMBER_ARM1136: + case PART_NUMBER_ARM1156: + case PART_NUMBER_ARM1176: ret = armv6pmu_init(pmu); break; - case 0xB020: /* ARM11mpcore */ + case PART_NUMBER_ARM11MPCORE: ret = armv6mpcore_pmu_init(pmu); break; - case 0xC080: /* Cortex-A8 */ + case PART_NUMBER_CORTEX_A8: ret = armv7_a8_pmu_init(pmu); break; - case 0xC090: /* Cortex-A9 */ + case PART_NUMBER_CORTEX_A9: ret = armv7_a9_pmu_init(pmu); break; - case 0xC050: /* Cortex-A5 */ + case PART_NUMBER_CORTEX_A5: ret = armv7_a5_pmu_init(pmu); break; - case 0xC0F0: /* Cortex-A15 */ + case PART_NUMBER_CORTEX_A15: ret = armv7_a15_pmu_init(pmu); break; - case 0xC070: /* Cortex-A7 */ + break; + case PART_NUMBER_CORTEX_A7: ret = armv7_a7_pmu_init(pmu); break; } /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { + } else if (implementor == IMPLEMENTOR_INTEL) { part_number = (cpuid >> 13) & 0x7; switch (part_number) { - case 1: + case PART_NUMBER_XSCALE1: ret = xscale1pmu_init(pmu); break; - case 2: + case PART_NUMBER_XSCALE2: ret = xscale2pmu_init(pmu); break; }