From patchwork Mon Dec 10 22:08:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 1860351 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 1E5CCDFB79 for ; Mon, 10 Dec 2012 22:12:52 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TiBWr-0001Rl-Tj; Mon, 10 Dec 2012 22:08:50 +0000 Received: from mail.free-electrons.com ([88.190.12.23]) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TiBWl-0001RA-RG for linux-arm-kernel@lists.infradead.org; Mon, 10 Dec 2012 22:08:44 +0000 Received: by mail.free-electrons.com (Postfix, from userid 106) id DB08D18D; Mon, 10 Dec 2012 23:08:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00, UPPERCASE_50_75 shortcircuit=no autolearn=no version=3.3.1 Received: from localhost (gar31-2-82-226-185-134.fbx.proxad.net [82.226.185.134]) by mail.free-electrons.com (Postfix) with ESMTPSA id C386912B; Mon, 10 Dec 2012 23:08:29 +0100 (CET) From: Maxime Ripard To: Arnd Bergmann , Olof Johansson Subject: [PATCH 2/6] ARM: pinctrl: sunxi: Add the pinctrl pin set for sun5i Date: Mon, 10 Dec 2012 23:08:17 +0100 Message-Id: <1355177301-31928-3-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355177301-31928-1-git-send-email-maxime.ripard@free-electrons.com> References: <1355177301-31928-1-git-send-email-maxime.ripard@free-electrons.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121210_170844_243917_8A53D93B X-CRM114-Status: GOOD ( 11.97 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 UPPERCASE_50_75 message body is 50-75% uppercase Cc: Alejandro Mery , Stefan Roese , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Since the Allwinner SoCs variants don't have the same set of pins to handle, we need to declare the pin ranges available. Signed-off-by: Maxime Ripard --- drivers/pinctrl/pinctrl-sunxi.c | 120 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index 1da6d3e..df7e3b7 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c @@ -26,6 +26,125 @@ #include "core.h" #include "pinctrl-sunxi.h" +static const struct pinctrl_pin_desc sun5i_pinctrl_pins[] = { + /* Hole */ + SUNXI_PINCTRL_PIN_PB0, + SUNXI_PINCTRL_PIN_PB1, + SUNXI_PINCTRL_PIN_PB2, + SUNXI_PINCTRL_PIN_PB3, + SUNXI_PINCTRL_PIN_PB4, + /* Hole */ + SUNXI_PINCTRL_PIN_PB10, + /* Hole */ + SUNXI_PINCTRL_PIN_PB15, + SUNXI_PINCTRL_PIN_PB16, + SUNXI_PINCTRL_PIN_PB17, + SUNXI_PINCTRL_PIN_PB18, + /* Hole */ + SUNXI_PINCTRL_PIN_PC0, + SUNXI_PINCTRL_PIN_PC1, + SUNXI_PINCTRL_PIN_PC2, + SUNXI_PINCTRL_PIN_PC3, + SUNXI_PINCTRL_PIN_PC4, + SUNXI_PINCTRL_PIN_PC5, + SUNXI_PINCTRL_PIN_PC6, + SUNXI_PINCTRL_PIN_PC7, + SUNXI_PINCTRL_PIN_PC8, + SUNXI_PINCTRL_PIN_PC9, + SUNXI_PINCTRL_PIN_PC10, + SUNXI_PINCTRL_PIN_PC11, + SUNXI_PINCTRL_PIN_PC12, + SUNXI_PINCTRL_PIN_PC13, + SUNXI_PINCTRL_PIN_PC14, + SUNXI_PINCTRL_PIN_PC15, + /* Hole */ + SUNXI_PINCTRL_PIN_PC19, + /* Hole */ + SUNXI_PINCTRL_PIN_PD2, + SUNXI_PINCTRL_PIN_PD3, + SUNXI_PINCTRL_PIN_PD4, + SUNXI_PINCTRL_PIN_PD5, + SUNXI_PINCTRL_PIN_PD6, + SUNXI_PINCTRL_PIN_PD7, + /* Hole */ + SUNXI_PINCTRL_PIN_PD10, + SUNXI_PINCTRL_PIN_PD11, + SUNXI_PINCTRL_PIN_PD12, + SUNXI_PINCTRL_PIN_PD13, + SUNXI_PINCTRL_PIN_PD14, + SUNXI_PINCTRL_PIN_PD15, + /* Hole */ + SUNXI_PINCTRL_PIN_PD18, + SUNXI_PINCTRL_PIN_PD19, + SUNXI_PINCTRL_PIN_PD20, + SUNXI_PINCTRL_PIN_PD21, + SUNXI_PINCTRL_PIN_PD22, + SUNXI_PINCTRL_PIN_PD23, + SUNXI_PINCTRL_PIN_PD24, + SUNXI_PINCTRL_PIN_PD25, + SUNXI_PINCTRL_PIN_PD26, + SUNXI_PINCTRL_PIN_PD27, + /* Hole */ + SUNXI_PINCTRL_PIN_PE0, + SUNXI_PINCTRL_PIN_PE1, + SUNXI_PINCTRL_PIN_PE2, + SUNXI_PINCTRL_PIN_PE3, + SUNXI_PINCTRL_PIN_PE4, + SUNXI_PINCTRL_PIN_PE5, + SUNXI_PINCTRL_PIN_PE6, + SUNXI_PINCTRL_PIN_PE7, + SUNXI_PINCTRL_PIN_PE8, + SUNXI_PINCTRL_PIN_PE9, + SUNXI_PINCTRL_PIN_PE10, + SUNXI_PINCTRL_PIN_PE11, + /* Hole */ + SUNXI_PINCTRL_PIN_PF0, + SUNXI_PINCTRL_PIN_PF1, + SUNXI_PINCTRL_PIN_PF2, + SUNXI_PINCTRL_PIN_PF3, + SUNXI_PINCTRL_PIN_PF4, + SUNXI_PINCTRL_PIN_PF5, + /* Hole */ + SUNXI_PINCTRL_PIN_PG0, + SUNXI_PINCTRL_PIN_PG1, + SUNXI_PINCTRL_PIN_PG2, + SUNXI_PINCTRL_PIN_PG3, + SUNXI_PINCTRL_PIN_PG4, + /* Hole */ + SUNXI_PINCTRL_PIN_PG9, + SUNXI_PINCTRL_PIN_PG10, + SUNXI_PINCTRL_PIN_PG11, + SUNXI_PINCTRL_PIN_PG12, +}; + +static struct pinctrl_gpio_range sun5i_pinctrl_ranges[] = { + /* PB */ + SUNXI_GPIO_RANGE(1, 32, 5), + SUNXI_GPIO_RANGE(2, 42, 1), + SUNXI_GPIO_RANGE(3, 47, 4), + /* PC */ + SUNXI_GPIO_RANGE(4, 64, 16), + SUNXI_GPIO_RANGE(5, 83, 1), + /* PD */ + SUNXI_GPIO_RANGE(6, 98, 8), + SUNXI_GPIO_RANGE(7, 106, 6), + SUNXI_GPIO_RANGE(8, 114, 10), + /* PE */ + SUNXI_GPIO_RANGE(9, 128, 12), + /* PF */ + SUNXI_GPIO_RANGE(10, 160, 6), + /* PG */ + SUNXI_GPIO_RANGE(11, 192, 5), + SUNXI_GPIO_RANGE(12, 201, 4), +}; + +static const struct sunxi_pinctrl_data sun5i_pinctrl_data = { + .ranges = sun5i_pinctrl_ranges, + .nranges = ARRAY_SIZE(sun5i_pinctrl_ranges), + .pins = sun5i_pinctrl_pins, + .npins = ARRAY_SIZE(sun5i_pinctrl_pins), +}; + static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) { struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); @@ -251,6 +370,7 @@ static struct pinctrl_desc sunxi_pctrl_desc = { }; static struct of_device_id sunxi_pinctrl_match[] __devinitconst = { + { .compatible = "allwinner,sun5i-pinctrl", .data = (void *)&sun5i_pinctrl_data }, {} }; MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);