From patchwork Wed Dec 12 21:43:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Hunter, Jon" X-Patchwork-Id: 1875701 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 7E3B43FC81 for ; Thu, 13 Dec 2012 17:22:15 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TjCQg-0003Ht-NN; Thu, 13 Dec 2012 17:18:38 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tiu6c-0003A8-GJ for linux-arm-kernel@lists.infradead.org; Wed, 12 Dec 2012 21:44:43 +0000 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id qBCLiVlQ017316; Wed, 12 Dec 2012 15:44:31 -0600 Received: from DLEE74.ent.ti.com (dlee74.ent.ti.com [157.170.170.8]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id qBCLiVVb031932; Wed, 12 Dec 2012 15:44:31 -0600 Received: from dlelxv23.itg.ti.com (172.17.1.198) by DLEE74.ent.ti.com (157.170.170.8) with Microsoft SMTP Server id 14.1.323.3; Wed, 12 Dec 2012 15:44:31 -0600 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv23.itg.ti.com (8.13.8/8.13.8) with ESMTP id qBCLiU6q031503; Wed, 12 Dec 2012 15:44:30 -0600 Received: from localhost (ula0741266.am.dhcp.ti.com [192.157.144.139]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id qBCLiUw10500; Wed, 12 Dec 2012 15:44:30 -0600 (CST) From: Jon Hunter To: Russell King , Will Deacon , Grant Likely , Rob Herring Subject: [RFC 1/5] ARM: CORESIGHT: Add generic lock/unlock helpers Date: Wed, 12 Dec 2012 15:43:04 -0600 Message-ID: <1355348588-22318-2-git-send-email-jon-hunter@ti.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1355348588-22318-1-git-send-email-jon-hunter@ti.com> References: <1355348588-22318-1-git-send-email-jon-hunter@ti.com> MIME-Version: 1.0 X-Bad-Reply: References and In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121212_164442_819331_BC1DA305 X-CRM114-Status: GOOD ( 12.25 ) X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.152 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-Mailman-Approved-At: Thu, 13 Dec 2012 12:18:34 -0500 Cc: Paul Walmsley , device-tree , Jon Hunter , Ming Lei , linux-omap , Pratik Patel , Linus Walleij , linux-arm X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The Cross Trigger Interface (CTI) helpers in cti.h include definitions for the Coresight Lock Access Register (LAR) and Lock Status Register (LSR). These registers are already defined in coresight.h and so rather than having multiple definitions, just use the definitions from coresight.h. Add the following coresight macros ... - coresight_unlock() --> Unlocks coresight module - coresight_lock() --> Locks coresight module Use the above macros for ETB, ETM and CTI. The do-while(0) statement has been removed from the macro as it is not a multi-line macro. Signed-off-by: Jon Hunter --- arch/arm/include/asm/cti.h | 16 +++------------- arch/arm/include/asm/hardware/coresight.h | 16 ++++++++-------- 2 files changed, 11 insertions(+), 21 deletions(-) diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h index f2e5cad..00add00 100644 --- a/arch/arm/include/asm/cti.h +++ b/arch/arm/include/asm/cti.h @@ -2,6 +2,7 @@ #define __ASMARM_CTI_H #include +#include /* The registers' definition is from section 3.2 of * Embedded Cross Trigger Revision: r0p0 @@ -29,17 +30,6 @@ #define CTIPCELLID2 0xFF8 #define CTIPCELLID3 0xFFC -/* The below are from section 3.6.4 of - * CoreSight v1.0 Architecture Specification - */ -#define LOCKACCESS 0xFB0 -#define LOCKSTATUS 0xFB4 - -/* write this value to LOCKACCESS will unlock the module, and - * other value will lock the module - */ -#define LOCKCODE 0xC5ACCE55 - /** * struct cti - cross trigger interface struct * @base: mapped virtual address for the cti base @@ -146,7 +136,7 @@ static inline void cti_irq_ack(struct cti *cti) */ static inline void cti_unlock(struct cti *cti) { - __raw_writel(LOCKCODE, cti->base + LOCKACCESS); + coresight_unlock(cti->base); } /** @@ -158,6 +148,6 @@ static inline void cti_unlock(struct cti *cti) */ static inline void cti_lock(struct cti *cti) { - __raw_writel(~LOCKCODE, cti->base + LOCKACCESS); + coresight_lock(cti->base); } #endif diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h index 7ecd793..dcd0e66 100644 --- a/arch/arm/include/asm/hardware/coresight.h +++ b/arch/arm/include/asm/hardware/coresight.h @@ -141,17 +141,17 @@ #define ETBFF_TRIGEVT BIT(9) #define ETBFF_TRIGFL BIT(10) -#define etb_writel(t, v, x) \ - (__raw_writel((v), (t)->etb_regs + (x))) +#define etb_writel(t, v, x) (__raw_writel((v), (t)->etb_regs + (x))) #define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x))) -#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0) -#define etm_unlock(t) \ - do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) +#define etb_lock(t) coresight_lock((t)->etb_regs) +#define etb_unlock(t) coresight_unlock((t)->etb_regs) +#define etm_lock(t) coresight_lock((t)->etm_regs) +#define etm_unlock(t) coresight_unlock((t)->etm_regs) -#define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0) -#define etb_unlock(t) \ - do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0) +#define coresight_lock(base) (__raw_writel(0, base + CSMR_LOCKACCESS)) +#define coresight_unlock(base) \ + (__raw_writel(UNLOCK_MAGIC, base + CSMR_LOCKACCESS)) #endif /* __ASM_HARDWARE_CORESIGHT_H */