@@ -38,3 +38,17 @@ Example:
reg = <0x12120000 0x100>;
interrupts = <0 71 0>;
};
+
+DWC3
+Required properties:
+ - compatible: should be "samsung,exynos5250-dwc3" for USB 3.0 DWC3 controller.
+ - reg: physical base address of the controller and length of memory mapped
+ region.
+ - interrupts: interrupt number to the cpu.
+
+Example:
+ usb@12000000 {
+ compatible = "samsung,exynos5250-dwc3";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ };
@@ -299,6 +299,12 @@
rx-dma-channel = <&pdma0 11>; /* preliminary */
};
+ usb@12000000 {
+ compatible = "samsung,exynos5250-dwc3";
+ reg = <0x12000000 0x10000>;
+ interrupts = <0 72 0>;
+ };
+
usb@12110000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12110000 0x100>;
@@ -426,6 +426,7 @@ config MACH_EXYNOS5_DT
depends on ARCH_EXYNOS5
select ARM_AMBA
select USE_OF
+ select USB_ARCH_HAS_XHCI
help
Machine support for Samsung EXYNOS5 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS5 SoC based board.
@@ -768,6 +768,11 @@ static struct clk exynos5_init_clocks_off[] = {
.enable = exynos5_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 18),
}, {
+ .name = "usbdrd30",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 19),
+ }, {
.name = "usbotg",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
@@ -1121,6 +1126,16 @@ static struct clksrc_sources exynos5_clkset_group = {
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
};
+struct clk *exynos5_clkset_usbdrd30_list[] = {
+ [0] = &exynos5_clk_mout_mpll.clk,
+ [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+struct clksrc_sources exynos5_clkset_usbdrd30 = {
+ .sources = exynos5_clkset_usbdrd30_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_usbdrd30_list),
+};
+
/* Possible clock sources for aclk_266_gscl_sub Mux */
static struct clk *clk_src_gscl_266_list[] = {
[0] = &clk_ext_xtal_mux,
@@ -1415,6 +1430,15 @@ static struct clksrc_clk exynos5_clksrcs[] = {
.parent = &exynos5_clk_mout_cpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+ }, {
+ .clk = {
+ .name = "sclk_usbdrd30",
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &exynos5_clkset_usbdrd30,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 28, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 24, .size = 4 },
},
};
@@ -201,6 +201,7 @@
#define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_OHCI 0x12590000
#define EXYNOS4_PA_HSPHY 0x125B0000
+#define EXYNOS5_PA_DRD 0x12000000
#define EXYNOS5_PA_EHCI 0x12110000
#define EXYNOS5_PA_OHCI 0x12120000
#define EXYNOS4_PA_MFC 0x13400000
@@ -114,6 +114,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
"s5p-ehci", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-ohci", EXYNOS5_PA_OHCI,
"exynos-ohci", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5250-dwc3", EXYNOS5_PA_DRD,
+ "exynos-dwc3", NULL),
{},
};
Adding DWC3 device tree node for Exynos5250 along with the device address and clock support needed for the controller. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> --- Changes from v2: - Changed the compatible string to chip specific(samsung,exynos5250), since dwc3-exynos is being used from exynso5250 onwards. - Based on changes for USB 2.0: https://lists.ozlabs.org/pipermail/devicetree-discuss/2012-December/024413.html Changes from v1: - Changed the device node name from 'dwc3' to 'usb@12000000'. - Added the documentation for device tree bindings for dwc3 controller. .../devicetree/bindings/usb/exynos-usb.txt | 14 +++++++++++ arch/arm/boot/dts/exynos5250.dtsi | 6 +++++ arch/arm/mach-exynos/Kconfig | 1 + arch/arm/mach-exynos/clock-exynos5.c | 24 ++++++++++++++++++++ arch/arm/mach-exynos/include/mach/map.h | 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 2 + 6 files changed, 48 insertions(+), 0 deletions(-)