From patchwork Mon Dec 17 06:18:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 1886021 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 803BA3FCA5 for ; Mon, 17 Dec 2012 06:21:35 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TkU2A-0004J1-OM; Mon, 17 Dec 2012 06:18:38 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TkU26-0004Il-UT for linux-arm-kernel@lists.infradead.org; Mon, 17 Dec 2012 06:18:35 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Sun, 16 Dec 2012 22:22:00 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Sun, 16 Dec 2012 22:16:19 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Sun, 16 Dec 2012 22:16:19 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.279.1; Sun, 16 Dec 2012 22:18:27 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Sun, 16 Dec 2012 22:18:40 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id qBH6INSC022585; Sun, 16 Dec 2012 22:18:24 -0800 (PST) From: Hiroshi Doyu To: Subject: [PATCH 1/4] ARM: dt: Add doc for ARM Snoop Control Unit(SCU) Date: Mon, 17 Dec 2012 08:18:01 +0200 Message-ID: <1355725087-11363-1-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121217_011835_161081_6C485AA3 X-CRM114-Status: UNSURE ( 9.09 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Russell King , Stephen Warren , devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Grant Likely , Rob Landley , linux-tegra@vger.kernel.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add scu.txt under arm for ARM Snoop Control Unit(SCU) Signed-off-by: Hiroshi Doyu --- Documentation/devicetree/bindings/arm/scu.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/scu.txt diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt new file mode 100644 index 0000000..96264cf --- /dev/null +++ b/Documentation/devicetree/bindings/arm/scu.txt @@ -0,0 +1,15 @@ +* ARM Snoop Control Unit(SCU) + +ARM cores often have a configurable SCU to the memory system through +the AXI interfaces. + +Required properties: + +- compatible : "arm,cortex-a9-scu" +- reg : Specifies base physical address and size of the SCU registers. + +Example: + scu { + compatible = "arm,cortex-a9-scu"; + reg = <0x50040000 0x58>; + };