From patchwork Mon Dec 17 06:18:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 1886031 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id F1D1DDF266 for ; Mon, 17 Dec 2012 06:21:35 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TkU2e-0004NK-VY; Mon, 17 Dec 2012 06:19:09 +0000 Received: from hqemgate03.nvidia.com ([216.228.121.140]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TkU2R-0004LB-Lr for linux-arm-kernel@lists.infradead.org; Mon, 17 Dec 2012 06:18:56 +0000 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Sun, 16 Dec 2012 22:22:16 -0800 Received: from hqemhub03.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Sun, 16 Dec 2012 22:18:44 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Sun, 16 Dec 2012 22:18:44 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.279.1; Sun, 16 Dec 2012 22:18:44 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Sun, 16 Dec 2012 22:18:57 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id qBH6INSF022585; Sun, 16 Dec 2012 22:18:42 -0800 (PST) From: Hiroshi Doyu To: Subject: [PATCH 4/4] ARM: tegra: Set SCU base address dynamically from DT Date: Mon, 17 Dec 2012 08:18:04 +0200 Message-ID: <1355725087-11363-4-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355725087-11363-1-git-send-email-hdoyu@nvidia.com> References: <1355725087-11363-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121217_011855_885488_B19AB86F X-CRM114-Status: GOOD ( 15.04 ) X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.140 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Russell King , Stephen Warren , devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Grant Likely , Rob Landley , linux-tegra@vger.kernel.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Set Snoop Control Unit(SCU) register base address dynamically from DT. Signed-off-by: Hiroshi Doyu --- arch/arm/mach-tegra/platsmp.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 1b926df..45c0b79 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include #include @@ -36,7 +38,7 @@ extern void tegra_secondary_startup(void); -static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); +static void __iomem *scu_base; #define EVP_CPU_RESET_VECTOR \ (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) @@ -143,14 +145,28 @@ done: return status; } +static const struct of_device_id cortex_a9_scu_match[] __initconst = { + { .compatible = "arm,cortex-a9-scu", }, + {} +}; + /* * Initialise the CPU possible map early - this describes the CPUs * which may be present or become present in the system. */ static void __init tegra_smp_init_cpus(void) { - unsigned int i, ncores = scu_get_core_count(scu_base); + struct device_node *np; + unsigned int i, ncores = 1; + + np = of_find_matching_node(NULL, cortex_a9_scu_match); + if (!np) + return; + scu_base = of_iomap(np, 0); + if (!scu_base) + return; + ncores = scu_get_core_count(scu_base); if (ncores > nr_cpu_ids) { pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", ncores, nr_cpu_ids); @@ -166,7 +182,8 @@ static void __init tegra_smp_init_cpus(void) static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) { tegra_cpu_reset_handler_init(); - scu_enable(scu_base); + if (scu_base) + scu_enable(scu_base); } struct smp_operations tegra_smp_ops __initdata = {