From patchwork Tue Dec 18 04:06:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christoffer Dall X-Patchwork-Id: 1890011 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id AC6D53FC64 for ; Tue, 18 Dec 2012 04:09:47 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TkoSN-000493-1o; Tue, 18 Dec 2012 04:07:03 +0000 Received: from mail-vb0-f52.google.com ([209.85.212.52]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TkoSI-00048d-Gt for linux-arm-kernel@lists.infradead.org; Tue, 18 Dec 2012 04:07:00 +0000 Received: by mail-vb0-f52.google.com with SMTP id ez10so240149vbb.25 for ; Mon, 17 Dec 2012 20:06:57 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=eoZmqBmvv7yld1h1tbOM/OGZuGAn8H4XDluF90JBITc=; b=V3IMpz4ZUoDSuX5xiL4NQoo60vo1Y4Qb8SDZfvMBJKP2ParzDGTbofNaCegxBanWkZ qMEInugfw5JcfnGf6fwDiwcriO8fWLtgmM8TEh2K5k78kGiFbP4ZDqgMDoGXN53eih36 9PSyHJTPHiQtUp6HlNNCG+PfSXv7fjUCtipOhHvU4Ug4X0/GW8ajPWRqsIGiMq4fnNpx uWvYuQ6JujQk76wcPDddzGszibi9qo9AlSsKoovoCv4ETmgfKEABroLzEFdiUkWLBIm7 u9kSuopym8ZcaIvqV+bBTQiKkRhc3THbx8pJ9xVLgDJtNcvw5SQygwos5sfBE1RwRo33 8Xwg== X-Received: by 10.220.210.193 with SMTP id gl1mr850603vcb.58.1355803617047; Mon, 17 Dec 2012 20:06:57 -0800 (PST) Received: from localhost.localdomain (pool-72-80-83-148.nycmny.fios.verizon.net. [72.80.83.148]) by mx.google.com with ESMTPS id b10sm592695vdk.15.2012.12.17.20.06.55 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 17 Dec 2012 20:06:55 -0800 (PST) From: Christoffer Dall To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] ARM: Use implementor and part defines from cputype.h Date: Mon, 17 Dec 2012 23:06:38 -0500 Message-Id: <1355803598-58471-2-git-send-email-c.dall@virtualopensystems.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355803598-58471-1-git-send-email-c.dall@virtualopensystems.com> References: <1355803598-58471-1-git-send-email-c.dall@virtualopensystems.com> X-Gm-Message-State: ALoCoQkJaZZKZtF21SVhPjt+JA4txghMpasYmakfXO5kD9GoxcoInjxCAuUZhxqenJ0FSwYtxK1f X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121217_230658_722154_87780B20 X-CRM114-Status: GOOD ( 13.67 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.52 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Will Deacon , Christoffer Dall , Russell King , kvmarm@lists.cs.columbia.edu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Instead of decoding implementor numbers, part numbers and Xscale architecture masks inline in the pmu probing function, use defines and accessor functions from cputype.h, which can also be shared by other subsystems, such as KVM. Cc: Russell King Cc: Will Deacon Signed-off-by: Christoffer Dall --- arch/arm/kernel/perf_event_cpu.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c index 9a4f630..5c59e19 100644 --- a/arch/arm/kernel/perf_event_cpu.c +++ b/arch/arm/kernel/perf_event_cpu.c @@ -201,48 +201,46 @@ static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = { static int __devinit probe_current_pmu(struct arm_pmu *pmu) { int cpu = get_cpu(); - unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); + unsigned long implementor = read_cpuid_implementor(); + unsigned long part_number = read_cpuid_part_number(); int ret = -ENODEV; pr_info("probing PMU on CPU %d\n", cpu); /* ARM Ltd CPUs. */ - if (0x41 == implementor) { + if (implementor == ARM_CPU_IMP_ARM) { switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ + case ARM_CPU_PART_ARM1136: + case ARM_CPU_PART_ARM1156: + case ARM_CPU_PART_ARM1176: ret = armv6pmu_init(pmu); break; - case 0xB020: /* ARM11mpcore */ + case ARM_CPU_PART_ARM11MPCORE: ret = armv6mpcore_pmu_init(pmu); break; - case 0xC080: /* Cortex-A8 */ + case ARM_CPU_PART_CORTEX_A8: ret = armv7_a8_pmu_init(pmu); break; - case 0xC090: /* Cortex-A9 */ + case ARM_CPU_PART_CORTEX_A9: ret = armv7_a9_pmu_init(pmu); break; - case 0xC050: /* Cortex-A5 */ + case ARM_CPU_PART_CORTEX_A5: ret = armv7_a5_pmu_init(pmu); break; - case 0xC0F0: /* Cortex-A15 */ + case ARM_CPU_PART_CORTEX_A15: ret = armv7_a15_pmu_init(pmu); break; - case 0xC070: /* Cortex-A7 */ + case ARM_CPU_PART_CORTEX_A7: ret = armv7_a7_pmu_init(pmu); break; } /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { - part_number = (cpuid >> 13) & 0x7; - switch (part_number) { - case 1: + } else if (implementor == ARM_CPU_IMP_INTEL) { + switch (xscale_cpu_arch_version()) { + case ARM_CPU_XSCALE_ARCH_V1: ret = xscale1pmu_init(pmu); break; - case 2: + case ARM_CPU_XSCALE_ARCH_V2: ret = xscale2pmu_init(pmu); break; }