From patchwork Tue Dec 18 19:19:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratik Patel X-Patchwork-Id: 1906401 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 5F16BDFB79 for ; Sat, 22 Dec 2012 20:50:31 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TmVxx-0007ba-6I; Sat, 22 Dec 2012 20:46:41 +0000 Received: from wolverine01.qualcomm.com ([199.106.114.254]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tl2nZ-0002nQ-ID for linux-arm-kernel@lists.infradead.org; Tue, 18 Dec 2012 19:26:00 +0000 X-IronPort-AV: E=Sophos;i="4.84,310,1355126400"; d="scan'208";a="14924758" Received: from pdmz-ns-snip_115_219.qualcomm.com (HELO mostmsg01.qualcomm.com) ([199.106.115.219]) by wolverine01.qualcomm.com with ESMTP/TLS/DHE-RSA-AES256-SHA; 18 Dec 2012 11:25:39 -0800 Received: from codeaurora.org (pdmz-ns-snip_218_1.qualcomm.com [192.168.218.1]) by mostmsg01.qualcomm.com (Postfix) with ESMTPA id 5C90F10004D7; Tue, 18 Dec 2012 11:25:39 -0800 (PST) From: pratikp@codeaurora.org To: linux-arm-kernel@lists.infradead.org Subject: [RFC 7/8] coresight: add CoreSight STM driver Date: Tue, 18 Dec 2012 11:19:24 -0800 Message-Id: <1355858365-11849-8-git-send-email-pratikp@codeaurora.org> X-Mailer: git-send-email 1.7.8.3 In-Reply-To: <1355858365-11849-1-git-send-email-pratikp@codeaurora.org> References: <1355858365-11849-1-git-send-email-pratikp@codeaurora.org> X-Bad-Reply: References and In-Reply-To but no 'Re:' in Subject. X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121218_142554_322032_42F50448 X-CRM114-Status: GOOD ( 22.16 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [199.106.114.254 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-Mailman-Approved-At: Sat, 22 Dec 2012 15:44:39 -0500 Cc: linux@arm.linux.org.uk, linus.walleij@linaro.org, will.deacon@arm.com, magnus.p.persson@stericsson.com, david.rusling@linaro.org, arve@android.com, dsaxena@linaro.org, john.stultz@linaro.org, jon-hunter@ti.com, d-deao@ti.com, christian.bejram@stericsson.com, Pratik Patel , devicetree-discuss@lists.ozlabs.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org From: Pratik Patel This driver manages CoreSight STM (System Trace Macrocell) and provides apis and user interface to support software instrumentation based tracing that takes advantage of the STM hardware. Signed-off-by: Pratik Patel --- drivers/coresight/Kconfig | 19 + drivers/coresight/Makefile | 1 + drivers/coresight/coresight-stm.c | 819 +++++++++++++++++++++++++++++++++++++ include/linux/coresight-stm.h | 51 +++ 4 files changed, 890 insertions(+), 0 deletions(-) create mode 100644 drivers/coresight/coresight-stm.c create mode 100644 include/linux/coresight-stm.h diff --git a/drivers/coresight/Kconfig b/drivers/coresight/Kconfig index 6905ef2..5a715e8 100644 --- a/drivers/coresight/Kconfig +++ b/drivers/coresight/Kconfig @@ -17,4 +17,23 @@ config CORESIGHT_LINKS_AND_SINKS responsible for transporting and collecting the trace data respectively. +config CORESIGHT_SOURCE_STM + bool "CoreSight System Trace Macrocell driver" + select CORESIGHT_LINKS_AND_SINKS + help + This driver provides support for hardware assisted software + instrumentation based tracing. This is primarily useful for + logging useful software events or data. + +config CORESIGHT_SOURCE_STM_DEFAULT_ENABLE + bool "Turn on CoreSight STM tracing by default" + depends on CORESIGHT_SOURCE_STM + help + Turns on CoreSight STM tracing (hardware assisted software + instrumentation based tracing) by default. Otherwise, tracing is + disabled by default but can be enabled via sysfs. + + If unsure, say 'N' here to avoid potential power, performance and + memory penalty. + endif diff --git a/drivers/coresight/Makefile b/drivers/coresight/Makefile index b385e81..750aa7c 100644 --- a/drivers/coresight/Makefile +++ b/drivers/coresight/Makefile @@ -4,3 +4,4 @@ obj-$(CONFIG_CORESIGHT) += coresight.o obj-$(CONFIG_OF) += of_coresight.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) += coresight-tmc.o coresight-tpiu.o coresight-etb.o coresight-funnel.o coresight-replicator.o +obj-$(CONFIG_CORESIGHT_SOURCE_STM) += coresight-stm.o diff --git a/drivers/coresight/coresight-stm.c b/drivers/coresight/coresight-stm.c new file mode 100644 index 0000000..69966ed --- /dev/null +++ b/drivers/coresight/coresight-stm.c @@ -0,0 +1,819 @@ +/* Copyright (c) 2012, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "coresight-priv.h" + +#define stm_writel(drvdata, val, off) __raw_writel((val), drvdata->base + off) +#define stm_readl(drvdata, off) __raw_readl(drvdata->base + off) + +#define STM_LOCK(drvdata) \ +do { \ + mb(); \ + stm_writel(drvdata, 0x0, CORESIGHT_LAR); \ +} while (0) +#define STM_UNLOCK(drvdata) \ +do { \ + stm_writel(drvdata, CORESIGHT_UNLOCK, CORESIGHT_LAR); \ + mb(); \ +} while (0) + +#define STMDMASTARTR (0xC04) +#define STMDMASTOPR (0xC08) +#define STMDMASTATR (0xC0C) +#define STMDMACTLR (0xC10) +#define STMDMAIDR (0xCFC) +#define STMHEER (0xD00) +#define STMHETER (0xD20) +#define STMHEMCR (0xD64) +#define STMHEMASTR (0xDF4) +#define STMHEFEAT1R (0xDF8) +#define STMHEIDR (0xDFC) +#define STMSPER (0xE00) +#define STMSPTER (0xE20) +#define STMSPSCR (0xE60) +#define STMSPMSCR (0xE64) +#define STMSPOVERRIDER (0xE68) +#define STMSPMOVERRIDER (0xE6C) +#define STMSPTRIGCSR (0xE70) +#define STMTCSR (0xE80) +#define STMTSSTIMR (0xE84) +#define STMTSFREQR (0xE8C) +#define STMSYNCR (0xE90) +#define STMAUXCR (0xE94) +#define STMSPFEAT1R (0xEA0) +#define STMSPFEAT2R (0xEA4) +#define STMSPFEAT3R (0xEA8) +#define STMITTRIGGER (0xEE8) +#define STMITATBDATA0 (0xEEC) +#define STMITATBCTR2 (0xEF0) +#define STMITATBID (0xEF4) +#define STMITATBCTR0 (0xEF8) + +#define NR_STM_CHANNEL (32) +#define BYTES_PER_CHANNEL (256) +#define STM_TRACE_BUF_SIZE (4096) +#define STM_USERSPACE_HEADER_SIZE (8) +#define STM_USERSPACE_MAGIC1_VAL (0xf0) +#define STM_USERSPACE_MAGIC2_VAL (0xf1) + +#define OST_START_TOKEN (0x30) +#define OST_VERSION (0x1) + +enum stm_pkt_type { + STM_PKT_TYPE_DATA = 0x98, + STM_PKT_TYPE_FLAG = 0xE8, + STM_PKT_TYPE_TRIG = 0xF8, +}; + +enum { + STM_OPTION_MARKED = 0x10, +}; + +#define stm_channel_addr(drvdata, ch) (drvdata->chs.base + \ + (ch * BYTES_PER_CHANNEL)) +#define stm_channel_off(type, opts) (type & ~opts) + +#ifdef CONFIG_CORESIGHT_SOURCE_STM_DEFAULT_ENABLE +static int boot_enable = 1; +#else +static int boot_enable; +#endif + +module_param_named( + boot_enable, boot_enable, int, S_IRUGO +); + +static int boot_nr_channel; + +module_param_named( + boot_nr_channel, boot_nr_channel, int, S_IRUGO +); + +struct channel_space { + void __iomem *base; + unsigned long *bitmap; +}; + +struct stm_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + struct miscdevice miscdev; + struct clk *clk; + spinlock_t spinlock; + struct channel_space chs; + bool enable; + DECLARE_BITMAP(entities, OST_ENTITY_MAX); +}; + +static struct stm_drvdata *stmdrvdata; + +static int stm_hwevent_isenable(struct stm_drvdata *drvdata) +{ + int ret = 0; + + spin_lock(&drvdata->spinlock); + if (drvdata->enable) + if (BVAL(stm_readl(drvdata, STMHEMCR), 0)) + ret = stm_readl(drvdata, STMHEER) == 0 ? 0 : 1; + spin_unlock(&drvdata->spinlock); + + return ret; +} + +static void __stm_hwevent_enable(struct stm_drvdata *drvdata) +{ + STM_UNLOCK(drvdata); + + /* + * Program STMHETER to ensure TRIGOUTHETE (fed to CTI) is asserted + * for HW events. + */ + stm_writel(drvdata, 0xFFFFFFFF, STMHETER); + stm_writel(drvdata, 0xFFFFFFFF, STMHEER); + stm_writel(drvdata, 0x5, STMHEMCR); + + STM_LOCK(drvdata); +} + +static int stm_hwevent_enable(struct stm_drvdata *drvdata) +{ + int ret = 0; + + spin_lock(&drvdata->spinlock); + if (drvdata->enable) + __stm_hwevent_enable(drvdata); + else + ret = -EINVAL; + spin_unlock(&drvdata->spinlock); + + return ret; +} + +static int stm_port_isenable(struct stm_drvdata *drvdata) +{ + int ret = 0; + + spin_lock(&drvdata->spinlock); + if (drvdata->enable) + ret = stm_readl(drvdata, STMSPER) == 0 ? 0 : 1; + spin_unlock(&drvdata->spinlock); + + return ret; +} + +static void __stm_port_enable(struct stm_drvdata *drvdata) +{ + STM_UNLOCK(drvdata); + + stm_writel(drvdata, 0x10, STMSPTRIGCSR); + stm_writel(drvdata, 0xFFFFFFFF, STMSPER); + + STM_LOCK(drvdata); +} + +static int stm_port_enable(struct stm_drvdata *drvdata) +{ + int ret = 0; + + spin_lock(&drvdata->spinlock); + if (drvdata->enable) + __stm_port_enable(drvdata); + else + ret = -EINVAL; + spin_unlock(&drvdata->spinlock); + + return ret; +} + +static void __stm_enable(struct stm_drvdata *drvdata) +{ + __stm_hwevent_enable(drvdata); + __stm_port_enable(drvdata); + + STM_UNLOCK(drvdata); + + stm_writel(drvdata, 0xFFF, STMSYNCR); + /* SYNCEN is read-only and HWTEN is not implemented */ + stm_writel(drvdata, 0x100003, STMTCSR); + + STM_LOCK(drvdata); +} + +static int stm_enable(struct coresight_device *csdev) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + int ret; + + ret = clk_prepare_enable(drvdata->clk); + if (ret) + return ret; + + spin_lock(&drvdata->spinlock); + __stm_enable(drvdata); + drvdata->enable = true; + spin_unlock(&drvdata->spinlock); + + dev_info(drvdata->dev, "STM tracing enabled\n"); + return 0; +} + +static void __stm_hwevent_disable(struct stm_drvdata *drvdata) +{ + STM_UNLOCK(drvdata); + + stm_writel(drvdata, 0x0, STMHEMCR); + stm_writel(drvdata, 0x0, STMHEER); + stm_writel(drvdata, 0x0, STMHETER); + + STM_LOCK(drvdata); +} + +static void stm_hwevent_disable(struct stm_drvdata *drvdata) +{ + spin_lock(&drvdata->spinlock); + if (drvdata->enable) + __stm_hwevent_disable(drvdata); + spin_unlock(&drvdata->spinlock); +} + +static void __stm_port_disable(struct stm_drvdata *drvdata) +{ + STM_UNLOCK(drvdata); + + stm_writel(drvdata, 0x0, STMSPER); + stm_writel(drvdata, 0x0, STMSPTRIGCSR); + + STM_LOCK(drvdata); +} + +static void stm_port_disable(struct stm_drvdata *drvdata) +{ + spin_lock(&drvdata->spinlock); + if (drvdata->enable) + __stm_port_disable(drvdata); + spin_unlock(&drvdata->spinlock); +} + +static void __stm_disable(struct stm_drvdata *drvdata) +{ + STM_UNLOCK(drvdata); + + stm_writel(drvdata, 0x100000, STMTCSR); + + STM_LOCK(drvdata); + + __stm_hwevent_disable(drvdata); + __stm_port_disable(drvdata); +} + +static void stm_disable(struct coresight_device *csdev) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock(&drvdata->spinlock); + __stm_disable(drvdata); + drvdata->enable = false; + spin_unlock(&drvdata->spinlock); + + /* Wait for 100ms so that pending data has been written to HW */ + msleep(100); + + clk_disable_unprepare(drvdata->clk); + + dev_info(drvdata->dev, "STM tracing disabled\n"); +} + +static const struct coresight_ops_source stm_source_ops = { + .enable = stm_enable, + .disable = stm_disable, +}; + +static const struct coresight_ops stm_cs_ops = { + .source_ops = &stm_source_ops, +}; + +static uint32_t stm_channel_alloc(uint32_t off) +{ + struct stm_drvdata *drvdata = stmdrvdata; + uint32_t ch; + + do { + ch = find_next_zero_bit(drvdata->chs.bitmap, + NR_STM_CHANNEL, off); + } while ((ch < NR_STM_CHANNEL) && + test_and_set_bit(ch, drvdata->chs.bitmap)); + + return ch; +} + +static void stm_channel_free(uint32_t ch) +{ + struct stm_drvdata *drvdata = stmdrvdata; + + clear_bit(ch, drvdata->chs.bitmap); +} + +static int stm_send(void *addr, const void *data, uint32_t size) +{ + uint64_t prepad = 0; + uint64_t postpad = 0; + char *pad; + uint8_t off, endoff; + uint32_t len = size; + + /* + * Only 64bit writes are supported. We rely on the compiler to + * generate STRD instruction for the casted 64bit assignments. + */ + + off = (unsigned long)data & 0x7; + + if (off) { + endoff = 8 - off; + pad = (char *)&prepad; + pad += off; + + while (endoff && size) { + *pad++ = *(char *)data++; + endoff--; + size--; + } + *(volatile uint64_t __force *)addr = prepad; + } + + /* Now we are 64bit aligned */ + while (size >= 8) { + *(volatile uint64_t __force *)addr = *(uint64_t *)data; + data += 8; + size -= 8; + } + + if (size) { + pad = (char *)&postpad; + + while (size) { + *pad++ = *(char *)data++; + size--; + } + *(volatile uint64_t __force *)addr = postpad; + } + + return roundup(len + off, 8); +} + +static int stm_trace_ost_header(unsigned long ch_addr, uint32_t options, + uint8_t entity_id, uint8_t proto_id, + const void *payload_data, uint32_t payload_size) +{ + void *addr; + uint8_t prepad_size; + uint64_t header; + char *hdr; + + hdr = (char *)&header; + + hdr[0] = OST_START_TOKEN; + hdr[1] = OST_VERSION; + hdr[2] = entity_id; + hdr[3] = proto_id; + prepad_size = (unsigned long)payload_data & 0x7; + *(uint32_t *)(hdr + 4) = (prepad_size << 24) | payload_size; + + /* For 64bit writes, header is expected to be of the D32M, D32M */ + options |= STM_OPTION_MARKED; + options &= ~STM_OPTION_TIMESTAMPED; + addr = (void *)(ch_addr | stm_channel_off(STM_PKT_TYPE_DATA, options)); + + return stm_send(addr, &header, sizeof(header)); +} + +static int stm_trace_data(unsigned long ch_addr, uint32_t options, + const void *data, uint32_t size) +{ + void *addr; + + options &= ~STM_OPTION_TIMESTAMPED; + addr = (void *)(ch_addr | stm_channel_off(STM_PKT_TYPE_DATA, options)); + + return stm_send(addr, data, size); +} + +static int stm_trace_ost_tail(unsigned long ch_addr, uint32_t options) +{ + void *addr; + uint64_t tail = 0x0; + + addr = (void *)(ch_addr | stm_channel_off(STM_PKT_TYPE_FLAG, options)); + + return stm_send(addr, &tail, sizeof(tail)); +} + +static inline int __stm_trace(uint32_t options, uint8_t entity_id, + uint8_t proto_id, const void *data, uint32_t size) +{ + struct stm_drvdata *drvdata = stmdrvdata; + int len = 0; + uint32_t ch; + unsigned long ch_addr; + + /* Allocate channel and get the channel address */ + ch = stm_channel_alloc(0); + ch_addr = (unsigned long)stm_channel_addr(drvdata, ch); + + /* Send the ost header */ + len += stm_trace_ost_header(ch_addr, options, entity_id, proto_id, data, + size); + + /* Send the payload data */ + len += stm_trace_data(ch_addr, options, data, size); + + /* Send the ost tail */ + len += stm_trace_ost_tail(ch_addr, options); + + /* We are done, free the channel */ + stm_channel_free(ch); + + return len; +} + +/** + * stm_trace - trace the binary or string data through STM + * @options: tracing options - guaranteed, timestamped, etc + * @entity_id: entity representing the trace data + * @proto_id: protocol id to distinguish between different binary formats + * @data: pointer to binary or string data buffer + * @size: size of data to send + * + * Packetizes the data as the payload to an OST packet and sends it over STM + * + * CONTEXT: + * Can be called from any context. + * + * RETURNS: + * number of bytes transfered over STM + */ +int stm_trace(uint32_t options, uint8_t entity_id, uint8_t proto_id, + const void *data, uint32_t size) +{ + struct stm_drvdata *drvdata = stmdrvdata; + + /* We don't support sizes more than 24bits (0 to 23) */ + if (!(drvdata && drvdata->enable && + test_bit(entity_id, drvdata->entities) && size && + (size < 0x1000000))) + return 0; + + return __stm_trace(options, entity_id, proto_id, data, size); +} +EXPORT_SYMBOL_GPL(stm_trace); + +static ssize_t stm_write(struct file *file, const char __user *data, + size_t size, loff_t *ppos) +{ + struct stm_drvdata *drvdata = container_of(file->private_data, + struct stm_drvdata, miscdev); + char *buf; + uint8_t entity_id, proto_id; + uint32_t options; + + if (!drvdata->enable || !size) + return -EINVAL; + + if (size > STM_TRACE_BUF_SIZE) + size = STM_TRACE_BUF_SIZE; + + buf = kmalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + if (copy_from_user(buf, data, size)) { + kfree(buf); + dev_dbg(drvdata->dev, "%s: copy_from_user failed\n", __func__); + return -EFAULT; + } + + if (size >= STM_USERSPACE_HEADER_SIZE && + buf[0] == STM_USERSPACE_MAGIC1_VAL && + buf[1] == STM_USERSPACE_MAGIC2_VAL) { + + entity_id = buf[2]; + proto_id = buf[3]; + options = *(uint32_t *)(buf + 4); + + if (!test_bit(entity_id, drvdata->entities) || + !(size - STM_USERSPACE_HEADER_SIZE)) { + kfree(buf); + return size; + } + + __stm_trace(options, entity_id, proto_id, + buf + STM_USERSPACE_HEADER_SIZE, + size - STM_USERSPACE_HEADER_SIZE); + } else { + if (!test_bit(OST_ENTITY_DEV_NODE, drvdata->entities)) { + kfree(buf); + return size; + } + + __stm_trace(STM_OPTION_TIMESTAMPED, OST_ENTITY_DEV_NODE, 0, + buf, size); + } + + kfree(buf); + + return size; +} + +static const struct file_operations stm_fops = { + .owner = THIS_MODULE, + .open = nonseekable_open, + .write = stm_write, + .llseek = no_llseek, +}; + +static ssize_t stm_show_hwevent_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val = stm_hwevent_isenable(drvdata); + + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t stm_store_hwevent_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + int ret = 0; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + if (val) + ret = stm_hwevent_enable(drvdata); + else + stm_hwevent_disable(drvdata); + + if (ret) + return ret; + return size; +} +static DEVICE_ATTR(hwevent_enable, S_IRUGO | S_IWUSR, stm_show_hwevent_enable, + stm_store_hwevent_enable); + +static ssize_t stm_show_port_enable(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val = stm_port_isenable(drvdata); + + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); +} + +static ssize_t stm_store_port_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val; + int ret = 0; + + if (sscanf(buf, "%lx", &val) != 1) + return -EINVAL; + + if (val) + ret = stm_port_enable(drvdata); + else + stm_port_disable(drvdata); + + if (ret) + return ret; + return size; +} +static DEVICE_ATTR(port_enable, S_IRUGO | S_IWUSR, stm_show_port_enable, + stm_store_port_enable); + +static ssize_t stm_show_entities(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); + ssize_t len; + + len = bitmap_scnprintf(buf, PAGE_SIZE, drvdata->entities, + OST_ENTITY_MAX); + + if (PAGE_SIZE - len < 2) + len = -EINVAL; + else + len += scnprintf(buf + len, 2, "\n"); + + return len; +} + +static ssize_t stm_store_entities(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent); + unsigned long val1, val2; + + if (sscanf(buf, "%lx %lx", &val1, &val2) != 2) + return -EINVAL; + + if (val1 >= OST_ENTITY_MAX) + return -EINVAL; + + if (val2) + __set_bit(val1, drvdata->entities); + else + __clear_bit(val1, drvdata->entities); + + return size; +} +static DEVICE_ATTR(entities, S_IRUGO | S_IWUSR, stm_show_entities, + stm_store_entities); + +static struct attribute *stm_attrs[] = { + &dev_attr_hwevent_enable.attr, + &dev_attr_port_enable.attr, + &dev_attr_entities.attr, + NULL, +}; + +static struct attribute_group stm_attr_grp = { + .attrs = stm_attrs, +}; + +static const struct attribute_group *stm_attr_grps[] = { + &stm_attr_grp, + NULL, +}; + +static int __devinit stm_probe(struct platform_device *pdev) +{ + int ret; + struct device *dev = &pdev->dev; + struct coresight_platform_data *pdata; + struct stm_drvdata *drvdata; + struct resource *res; + size_t res_size, bitmap_size; + struct coresight_desc *desc; + + if (pdev->dev.of_node) { + pdata = of_get_coresight_platform_data(dev, pdev->dev.of_node); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + pdev->dev.platform_data = pdata; + } + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + /* Store the driver data pointer for use in exported functions */ + stmdrvdata = drvdata; + drvdata->dev = &pdev->dev; + platform_set_drvdata(pdev, drvdata); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); + if (!drvdata->base) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) + return -ENODEV; + + if (boot_nr_channel) { + res_size = min((resource_size_t)(boot_nr_channel * + BYTES_PER_CHANNEL), resource_size(res)); + bitmap_size = boot_nr_channel * sizeof(long); + } else { + res_size = min((resource_size_t)(NR_STM_CHANNEL * + BYTES_PER_CHANNEL), resource_size(res)); + bitmap_size = NR_STM_CHANNEL * sizeof(long); + } + drvdata->chs.base = devm_ioremap(dev, res->start, res_size); + if (!drvdata->chs.base) + return -ENOMEM; + drvdata->chs.bitmap = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); + if (!drvdata->chs.bitmap) + return -ENOMEM; + + spin_lock_init(&drvdata->spinlock); + + drvdata->clk = devm_clk_get(dev, "core_clk"); + if (IS_ERR(drvdata->clk)) + return PTR_ERR(drvdata->clk); + + ret = clk_set_rate(drvdata->clk, CORESIGHT_CLK_RATE_TRACE); + if (ret) + return ret; + + bitmap_fill(drvdata->entities, OST_ENTITY_MAX); + + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); + if (!desc) + return -ENOMEM; + desc->type = CORESIGHT_DEV_TYPE_SOURCE; + desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE; + desc->ops = &stm_cs_ops; + desc->pdata = pdev->dev.platform_data; + desc->dev = &pdev->dev; + desc->groups = stm_attr_grps; + desc->owner = THIS_MODULE; + drvdata->csdev = coresight_register(desc); + if (IS_ERR(drvdata->csdev)) + return PTR_ERR(drvdata->csdev); + + drvdata->miscdev.name = ((struct coresight_platform_data *) + (pdev->dev.platform_data))->name; + drvdata->miscdev.minor = MISC_DYNAMIC_MINOR; + drvdata->miscdev.fops = &stm_fops; + ret = misc_register(&drvdata->miscdev); + if (ret) + goto err; + + dev_info(drvdata->dev, "STM initialized\n"); + + if (boot_enable) + coresight_enable(drvdata->csdev); + + return 0; +err: + coresight_unregister(drvdata->csdev); + return ret; +} + +static int __devexit stm_remove(struct platform_device *pdev) +{ + struct stm_drvdata *drvdata = platform_get_drvdata(pdev); + + misc_deregister(&drvdata->miscdev); + coresight_unregister(drvdata->csdev); + return 0; +} + +static struct of_device_id stm_match[] = { + {.compatible = "arm,coresight-stm"}, + {} +}; + +static struct platform_driver stm_driver = { + .probe = stm_probe, + .remove = __devexit_p(stm_remove), + .driver = { + .name = "coresight-stm", + .owner = THIS_MODULE, + .of_match_table = stm_match, + }, +}; + +static int __init stm_init(void) +{ + return platform_driver_register(&stm_driver); +} +module_init(stm_init); + +static void __exit stm_exit(void) +{ + platform_driver_unregister(&stm_driver); +} +module_exit(stm_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("CoreSight System Trace Macrocell driver"); diff --git a/include/linux/coresight-stm.h b/include/linux/coresight-stm.h new file mode 100644 index 0000000..15d6f8c --- /dev/null +++ b/include/linux/coresight-stm.h @@ -0,0 +1,51 @@ +#ifndef _LINUX_CORESIGHT_STM_H +#define _LINUX_CORESIGHT_STM_H + +enum { + OST_ENTITY_NONE = 0x00, + OST_ENTITY_FTRACE_EVENTS = 0x01, + OST_ENTITY_TRACE_PRINTK = 0x02, + OST_ENTITY_TRACE_MARKER = 0x04, + OST_ENTITY_DEV_NODE = 0x08, + OST_ENTITY_QVIEW = 0xFE, + OST_ENTITY_MAX = 0xFF, +}; + +enum { + STM_OPTION_NONE = 0x0, + STM_OPTION_TIMESTAMPED = 0x08, + STM_OPTION_GUARANTEED = 0x80, +}; + +#ifdef __KERNEL__ +#define stm_log_inv(entity_id, proto_id, data, size) \ + stm_trace(STM_OPTION_NONE, entity_id, proto_id, data, size) + +#define stm_log_inv_ts(entity_id, proto_id, data, size) \ + stm_trace(STM_OPTION_TIMESTAMPED, entity_id, proto_id, \ + data, size) + +#define stm_log_gtd(entity_id, proto_id, data, size) \ + stm_trace(STM_OPTION_GUARANTEED, entity_id, proto_id, \ + data, size) + +#define stm_log_gtd_ts(entity_id, proto_id, data, size) \ + stm_trace(STM_OPTION_GUARANTEED | STM_OPTION_TIMESTAMPED, \ + entity_id, proto_id, data, size) + +#define stm_log(entity_id, data, size) \ + stm_log_inv_ts(entity_id, 0, data, size) + +#ifdef CONFIG_CORESIGHT_SOURCE_STM +extern int stm_trace(uint32_t options, uint8_t entity_id, uint8_t proto_id, + const void *data, uint32_t size); +#else +static inline int stm_trace(uint32_t options, uint8_t entity_id, + uint8_t proto_id, const void *data, uint32_t size) +{ + return 0; +} +#endif +#endif /* __KERNEL__ */ + +#endif