From patchwork Thu Dec 20 09:44:04 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi DOYU X-Patchwork-Id: 1899181 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 28044DF23A for ; Thu, 20 Dec 2012 09:49:41 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TlciC-0006qe-MZ; Thu, 20 Dec 2012 09:46:45 +0000 Received: from hqemgate04.nvidia.com ([216.228.121.35]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tlchj-0006f1-Lm for linux-arm-kernel@lists.infradead.org; Thu, 20 Dec 2012 09:46:17 +0000 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Thu, 20 Dec 2012 01:45:44 -0800 Received: from hqemhub03.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 20 Dec 2012 01:43:34 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 20 Dec 2012 01:43:34 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.279.1; Thu, 20 Dec 2012 01:46:03 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Thu, 20 Dec 2012 01:46:20 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-25-186.nvidia.com [10.21.25.186]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id qBK9inJ9013509; Thu, 20 Dec 2012 01:45:59 -0800 (PST) From: Hiroshi Doyu To: Subject: [PATCH 6/9] ARM: dt: tegra114: Add new SoC base, Tegra 114 SoC Date: Thu, 20 Dec 2012 11:44:04 +0200 Message-ID: <1355996654-6579-7-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1355996654-6579-1-git-send-email-hdoyu@nvidia.com> References: <1355996654-6579-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20121220_044616_199857_CC5D58D6 X-CRM114-Status: GOOD ( 11.14 ) X-Spam-Score: -4.6 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [216.228.121.35 listed in list.dnswl.org] 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -0.7 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Andrew Lunn , Russell King , Jason Cooper , Stephen Warren , John Stultz , devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring , Grant Likely , Rob Landley , Olof Johansson , Thomas Gleixner , Shawn Guo , Jean-Christophe PLAGNIOL-VILLARD , linux-arm-kernel@lists.infradead.org, Hiroshi Doyu X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Initial support for Tegra 114 SoC. This is expected to be included in the board DTS files, Tegra 114 SoC based evaluation board family. Signed-off-by: Hiroshi Doyu --- arch/arm/boot/dts/tegra114.dtsi | 89 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 arch/arm/boot/dts/tegra114.dtsi diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi new file mode 100644 index 0000000..a5b7330 --- /dev/null +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -0,0 +1,89 @@ +/include/ "skeleton.dtsi" + +/ { + compatible = "nvidia,tegra114"; + interrupt-parent = <&gic>; + + gic: interrupt-controller { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + reg = <0x50041000 0x1000 + 0x50042000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer@60005000 { + compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; + reg = <0x60005000 0x400>; + interrupts = <0 0 0x04 + 0 1 0x04 + 0 41 0x04 + 0 42 0x04 + 0 121 0x04 + 0 122 0x04>; + }; + + serial@70006000 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = <0 36 0x04>; + status = "disabled"; + }; + + serial@70006040 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = <0 37 0x04>; + status = "disabled"; + }; + + serial@70006200 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = <0 46 0x04>; + status = "disabled"; + }; + + serial@70006300 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = <0 90 0x04>; + status = "disabled"; + }; + + serial@70006400 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = <0 91 0x04>; + status = "disabled"; + }; + + rtc { + compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = <0 2 0x04>; + }; + + pmc { + compatible = "nvidia,tegra114-pmc", "nvidia,tegra20-pmc"; + reg = <0x7000e400 0x400>; + }; + + tsc { + compatible = "nvidia,tegra114-tsc"; + reg = <0x700f0000 0x20000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; +};