From patchwork Thu Jan 10 08:35:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Chen X-Patchwork-Id: 1958661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 70BB03FF0F for ; Thu, 10 Jan 2013 08:39:52 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TtDcl-0001CS-K1; Thu, 10 Jan 2013 08:36:32 +0000 Received: from tx2ehsobe003.messaging.microsoft.com ([65.55.88.13] helo=tx2outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TtDcd-00018v-MN for linux-arm-kernel@lists.infradead.org; Thu, 10 Jan 2013 08:36:25 +0000 Received: from mail1-tx2-R.bigfish.com (10.9.14.237) by TX2EHSOBE010.bigfish.com (10.9.40.30) with Microsoft SMTP Server id 14.1.225.23; Thu, 10 Jan 2013 08:36:22 +0000 Received: from mail1-tx2 (localhost [127.0.0.1]) by mail1-tx2-R.bigfish.com (Postfix) with ESMTP id 26CA62A00C6; Thu, 10 Jan 2013 08:36:22 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1ee6h1de0h1202h1e76h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h1354h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1155h) Received: from mail1-tx2 (localhost.localdomain [127.0.0.1]) by mail1-tx2 (MessageSwitch) id 1357806979488797_4436; Thu, 10 Jan 2013 08:36:19 +0000 (UTC) Received: from TX2EHSMHS007.bigfish.com (unknown [10.9.14.254]) by mail1-tx2.bigfish.com (Postfix) with ESMTP id 70ADF1600B0; Thu, 10 Jan 2013 08:36:19 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS007.bigfish.com (10.9.99.107) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 10 Jan 2013 08:36:19 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.318.3; Thu, 10 Jan 2013 08:36:18 +0000 Received: from localhost.localdomain (nchen-desktop.ap.freescale.net [10.192.242.40]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r0A8ZtR5001462; Thu, 10 Jan 2013 01:35:57 -0700 From: Peter Chen To: , , , , , , , Subject: [PATCH 1/4] ARM: dts: mxs-phy: Change mxs phy clock usage Date: Thu, 10 Jan 2013 16:35:51 +0800 Message-ID: <1357806954-27960-1-git-send-email-peter.chen@freescale.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130110_033623_959804_51D09CDB X-CRM114-Status: GOOD ( 12.45 ) X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 3.0 KHOP_BIG_TO_CC Sent to 10+ recipients instaed of Bcc or a list -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [65.55.88.13 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: marex@denx.de, m.grzeschik@pengutronix.de, linux-doc@vger.kernel.org, matt@genesi-usa.com, devicetree-discuss@lists.ozlabs.org, linux-usb@vger.kernel.org, mkl@pengutronix.de, maxime.ripard@free-electrons.com, festevam@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org For mxs-phy user i.mx6q, the PHY's clock is controlled by hardware automatically, the software only needs to enable it at probe, this clock should be used like below: - Enable at mxs-phy's probe, and disable at mxs-phy's remove, so The clk framework doesn't need to know it. But other mxs-phy user mx28/mx23 may need it, so we give mxs-phy a dummy clock for imx6q. - During the runtime, we don't need to control it. Signed-off-by: Peter Chen --- .../devicetree/bindings/clock/imx6q-clock.txt | 2 -- Documentation/devicetree/bindings/usb/mxs-phy.txt | 2 ++ arch/arm/boot/dts/imx6q.dtsi | 10 +++++++--- arch/arm/mach-imx/clk-imx6q.c | 5 +---- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt index d77b4e6..5666486 100644 --- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt @@ -194,8 +194,6 @@ clocks and IDs. ssi2_ipg 179 ssi3_ipg 180 rom 181 - usbphy1 182 - usbphy2 183 ldb_di0_div_3_5 184 ldb_di1_div_3_5 185 sata_ref 186 diff --git a/Documentation/devicetree/bindings/usb/mxs-phy.txt b/Documentation/devicetree/bindings/usb/mxs-phy.txt index 5835b27..384e700 100644 --- a/Documentation/devicetree/bindings/usb/mxs-phy.txt +++ b/Documentation/devicetree/bindings/usb/mxs-phy.txt @@ -4,10 +4,12 @@ Required properties: - compatible: Should be "fsl,imx23-usbphy" - reg: Should contain registers location and length - interrupts: Should contain phy interrupt +- The reg offset for PHY clock at anatop Example: usbphy1: usbphy@020c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; + anatop-phy-reg-offset = <0x10>; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index d6265ca..d958c49 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -518,14 +518,18 @@ compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 0x04>; - clocks = <&clks 182>; - }; + anatop-phy-reg-offset = <0x10>; + /* the clk is controllered by hardware */ + clocks = <&clks 0>; + }; usbphy2: usbphy@020ca000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020ca000 0x1000>; interrupts = <0 45 0x04>; - clocks = <&clks 183>; + anatop-phy-reg-offset = <0x20>; + /* the clk is controllered by hardware */ + clocks = <&clks 0>; }; snvs@020cc000 { diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 7f2c10c..fa62bc9 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -153,7 +153,7 @@ enum mx6q_clks { ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, + ssi2_ipg, ssi3_ipg, rom, ldb_di0_div_3_5, ldb_di1_div_3_5, sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, clk_max }; @@ -208,9 +208,6 @@ int __init mx6q_clocks_init(void) clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0); - clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); - clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); - clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);