From patchwork Tue Jan 15 16:48:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: tip-bot for Dave Martin X-Patchwork-Id: 1979661 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 26CBDDF264 for ; Tue, 15 Jan 2013 16:53:02 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tv9hl-00050l-CC; Tue, 15 Jan 2013 16:49:41 +0000 Received: from mail-bk0-f41.google.com ([209.85.214.41]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tv9gt-0004pG-EF for linux-arm-kernel@lists.infradead.org; Tue, 15 Jan 2013 16:48:48 +0000 Received: by mail-bk0-f41.google.com with SMTP id jg9so201144bkc.28 for ; Tue, 15 Jan 2013 08:48:46 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=+vAn3CqmtXeFywmKhwWn80/QMh4KYXJUUmkdJmsJztI=; b=FhDhH3WQlLj++M/MFp3Js2XRSQcXiGkiTKeEJbUK4OKeuSBtcocRiw6OwyhmIGX17J c9PSRi570LEmH1FLxNrHAJrA/R6Jsd2nkGugMCl6V5EWzgBSi3FOMC/WUrJaNUZYgDIy coIzwjwqZbCSFMoczhMYzQjOUkF3YKizyMHRy5FAnqIcriC0G0bonWhcDnT9QTmjB24m gwz58yq6GHBwHBpNov3lMzKf1a2qO+n3GSoKeIZ7dzFvdinTksuNcdrYoDgX+OosH6oU 4tHETOn9fm+f8fYuxVxuzTbe6lkg37KapAFCRgJAXV9BlOQlC/ftMhtIopU1upgG2YOS pMqw== X-Received: by 10.205.139.16 with SMTP id iu16mr41937555bkc.88.1358268526115; Tue, 15 Jan 2013 08:48:46 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id 18sm13338796bkv.0.2013.01.15.08.48.44 (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 15 Jan 2013 08:48:45 -0800 (PST) From: Dave Martin To: Nicolas Pitre Subject: [RFC PATCH 4/4] ARM: vexpress/dcscb: power_up_setup memory barrier cleanup Date: Tue, 15 Jan 2013 16:48:18 +0000 Message-Id: <1358268498-8086-5-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1358268498-8086-1-git-send-email-dave.martin@linaro.org> References: <1358268498-8086-1-git-send-email-dave.martin@linaro.org> X-Gm-Message-State: ALoCoQkWLZ7A65cYbZyO1abDpPPPeXAbvnPzXeJfmL7sM5ZqkHEqA56ULMxFO68+hqVd8Ne3xP2Q X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130115_114847_725251_9AF7C617 X-CRM114-Status: UNSURE ( 9.67 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.214.41 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Achin Gupta , Will Deacon , Dave Martin , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The bL_head framework has sufficient barriers to ensure correct globally observed ordering of explicit memory accesses done by the power_up_setup function. This patch removes the unnecessary DSB from dcscb_setup.S. Signed-off-by: Dave Martin --- arch/arm/mach-vexpress/dcscb_setup.S | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S index c75ee8c..e338be7 100644 --- a/arch/arm/mach-vexpress/dcscb_setup.S +++ b/arch/arm/mach-vexpress/dcscb_setup.S @@ -64,14 +64,13 @@ ENTRY(dcscb_power_up_setup) ldr r3, =RTSM_CCI_PHYS_BASE - b 1f -0: dsb 1: ldr r0, [r3, #CCI_STATUS_OFFSET] tst r0, #STATUS_CHANGE_PENDING - bne 0b + bne 1b 2: @ Implementation-specific local CPU setup operations should go here, @ if any. In this case, there is nothing to do. bx lr + ENDPROC(dcscb_power_up_setup)