From patchwork Fri Jan 18 07:31:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 1999811 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 796EF3FD86 for ; Fri, 18 Jan 2013 07:39:02 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Tw6Uz-0000dv-Q7; Fri, 18 Jan 2013 07:36:27 +0000 Received: from mail-pa0-f54.google.com ([209.85.220.54]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Tw6Qs-0005h9-Av for linux-arm-kernel@lists.infradead.org; Fri, 18 Jan 2013 07:32:11 +0000 Received: by mail-pa0-f54.google.com with SMTP id bi5so1978687pad.41 for ; Thu, 17 Jan 2013 23:32:09 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=zq3WthXpFAVRi4EgKaqUgTo2llzVHUqIMlf3PJC43CU=; b=HK6RPXdSA/cvOZeIbUhsy1R5RZ3FwCthD4hsuMWRkT/OY1eEpqeJATVqEqbx/MNFWl yILQJUDjObsDcxT1s3YKWSc0gGwIFwEncXj6ZFu8qnEuopsPh7Z2kzEQ5NHuISZMzfXU 6IrjtrcwH//bsrlgGates63R0DoXw3ZT+KSgszUpoEiBUTBOnDLcU1UumtYplPFhWl7s baNumYolrIvpp7AE2D7pmvAT6gEQ8wnbcoDJ5qPVTm33MC9avWv7/HQDbmALEgEwd2nK CKCo/MxAdRXW7N7BvsPcKQY87mdhuj5Dszkzl87M02R2PTjf52X7mcsRwLfs3NgHdnap zogA== X-Received: by 10.68.130.195 with SMTP id og3mr21729799pbb.10.1358494329300; Thu, 17 Jan 2013 23:32:09 -0800 (PST) Received: from localhost.localdomain ([98.126.173.75]) by mx.google.com with ESMTPS id i6sm2922899paw.19.2013.01.17.23.32.06 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 17 Jan 2013 23:32:08 -0800 (PST) From: Haojian Zhuang To: linus.walleij@linaro.org, linux@arm.linux.org.uk, tony@atomide.com, linux-arm-kernel@lists.infradead.org, swarren@nvidia.com Subject: [PATCH v7 13/15] pinctrl: single: set function mask as optional Date: Fri, 18 Jan 2013 15:31:17 +0800 Message-Id: <1358494279-16503-14-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1358494279-16503-1-git-send-email-haojian.zhuang@linaro.org> References: <1358494279-16503-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQmyRPwpHdEp18NuoVNld+JyKha9H6LZM6yytNv6g06Jw53LyngCTcw/g9xiw2QqA4Snkx2q X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130118_023210_502525_3D12F49D X-CRM114-Status: GOOD ( 13.89 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.54 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Since Hisilicon's pin controller is divided into two parts. One is the function mux, and the other is pin configuration. These two parts are in the different memory regions. So make pinctrl-single,function-mask as optional property. Then we can define pingroups without valid function mux that is only used for pin configuration. Signed-off-by: Haojian Zhuang --- drivers/pinctrl/pinctrl-single.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 8b9dd95..fe8f321 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -350,6 +350,9 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, int i; pcs = pinctrl_dev_get_drvdata(pctldev); + /* If function mask is null, needn't enable it. */ + if (!pcs->fmask) + return 0; func = radix_tree_lookup(&pcs->ftree, fselector); if (!func) return -EINVAL; @@ -384,6 +387,10 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, int i; pcs = pinctrl_dev_get_drvdata(pctldev); + /* If function mask is null, needn't disable it. */ + if (!pcs->fmask) + return; + func = radix_tree_lookup(&pcs->ftree, fselector); if (!func) { dev_err(pcs->dev, "%s could not find function%i\n", @@ -427,6 +434,10 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, int mux_bytes = 0; unsigned data; + /* If function mask is null, return directly. */ + if (!pcs->fmask) + return -ENOTSUPP; + list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { frange = list_entry(pos, struct pcs_gpiofunc_range, node); if (pin >= frange->offset + frange->npins @@ -969,10 +980,17 @@ static int pcs_probe(struct platform_device *pdev) PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, "register width not specified\n"); - PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask, - "function register mask not specified\n"); - pcs->fshift = ffs(pcs->fmask) - 1; - pcs->fmax = pcs->fmask >> pcs->fshift; + ret = of_property_read_u32(np, "pinctrl-single,function-mask", + &pcs->fmask); + if (!ret) { + pcs->fshift = ffs(pcs->fmask) - 1; + pcs->fmax = pcs->fmask >> pcs->fshift; + } else { + /* If mask property doesn't exist, function mux is invalid. */ + pcs->fmask = 0; + pcs->fshift = 0; + pcs->fmax = 0; + } ret = of_property_read_u32(np, "pinctrl-single,function-off", &pcs->foff);