| Message ID | 1359313332-12305-2-git-send-email-maxime.ripard@free-electrons.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, Jan 27, 2013 at 8:02 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Since the pin controller of sunxi chips is represented as a single bank > in the driver. > Since this is neither convenient nor represented that way in the > datasheets, define a custom of_xlate function with the layout <bank pin > flag> > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> This does not apply and I only have 1/3 it seems? Sorry, help me understand which order these patches go in... Here is my allwinner branch: http://git.kernel.org/?p=linux/kernel/git/linusw/linux-pinctrl.git;a=shortlog;h=refs/heads/allwinner-sunxi Yours, Linus Walleij
Le 29/01/2013 23:41, Linus Walleij a écrit : > On Sun, Jan 27, 2013 at 8:02 PM, Maxime Ripard > <maxime.ripard@free-electrons.com> wrote: > >> Since the pin controller of sunxi chips is represented as a single bank >> in the driver. >> Since this is neither convenient nor represented that way in the >> datasheets, define a custom of_xlate function with the layout <bank pin >> flag> >> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > > This does not apply and I only have 1/3 it seems? > > Sorry, help me understand which order these patches go in... My bad, I forgot to mention the order of the patchsets, and to cc you for the all series... Sorry about that. This patch should come after the patch series that adds the support for the A10 SoCs in the pinctrl driver. Do you want me to resend this serie and cc you? Maxime
On Tue, Jan 29, 2013 at 11:54 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Le 29/01/2013 23:41, Linus Walleij a écrit : >> On Sun, Jan 27, 2013 at 8:02 PM, Maxime Ripard >> <maxime.ripard@free-electrons.com> wrote: >> >>> Since the pin controller of sunxi chips is represented as a single bank >>> in the driver. >>> Since this is neither convenient nor represented that way in the >>> datasheets, define a custom of_xlate function with the layout <bank pin >>> flag> >>> >>> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> >> >> This does not apply and I only have 1/3 it seems? >> >> Sorry, help me understand which order these patches go in... > > My bad, I forgot to mention the order of the patchsets, and to cc you > for the all series... Sorry about that. > > This patch should come after the patch series that adds the support for > the A10 SoCs in the pinctrl driver. I now tried to apply this on top of the A10 series and it *still* does not apply. > Do you want me to resend this serie and cc you? Please rebase these three on my allwinner branch: git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git allwinner-sunxi Seen here: http://git.kernel.org/?p=linux/kernel/git/linusw/linux-pinctrl.git;a=shortlog;h=refs/heads/allwinner-sunxi Yours, Linus Walleij
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c index 353f6a8..122eeca 100644 --- a/drivers/pinctrl/pinctrl-sunxi.c +++ b/drivers/pinctrl/pinctrl-sunxi.c @@ -1261,6 +1261,24 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, writel((value & DATA_PINS_MASK) << index, pctl->membase + reg); } +static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, + const struct of_phandle_args *gpiospec, + u32 *flags) +{ + int pin, base; + + base = PINS_PER_BANK * gpiospec->args[0]; + pin = base + gpiospec->args[1]; + + if (pin > (gc->base + gc->ngpio)) + return -EINVAL; + + if (flags) + *flags = gpiospec->args[2]; + + return pin; +} + static struct gpio_chip sunxi_pinctrl_gpio_chip __devinitconst = { .owner = THIS_MODULE, .request = sunxi_pinctrl_gpio_request, @@ -1269,6 +1287,8 @@ static struct gpio_chip sunxi_pinctrl_gpio_chip __devinitconst = { .direction_output = sunxi_pinctrl_gpio_direction_output, .get = sunxi_pinctrl_gpio_get, .set = sunxi_pinctrl_gpio_set, + .of_xlate = sunxi_pinctrl_gpio_of_xlate, + .of_gpio_n_cells = 3, .can_sleep = 0, };
Since the pin controller of sunxi chips is represented as a single bank in the driver. Since this is neither convenient nor represented that way in the datasheets, define a custom of_xlate function with the layout <bank pin flag> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> --- drivers/pinctrl/pinctrl-sunxi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)