From patchwork Wed Jan 30 22:33:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 2066651 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork2.kernel.org (Postfix) with ESMTP id 69516DF264 for ; Wed, 30 Jan 2013 09:36:27 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U0U3r-0004d8-L3; Wed, 30 Jan 2013 09:34:31 +0000 Received: from co1ehsobe005.messaging.microsoft.com ([216.32.180.188] helo=co1outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U0U3c-0004Xg-TP for linux-arm-kernel@lists.infradead.org; Wed, 30 Jan 2013 09:34:17 +0000 Received: from mail39-co1-R.bigfish.com (10.243.78.203) by CO1EHSOBE041.bigfish.com (10.243.66.106) with Microsoft SMTP Server id 14.1.225.23; Wed, 30 Jan 2013 09:34:15 +0000 Received: from mail39-co1 (localhost [127.0.0.1]) by mail39-co1-R.bigfish.com (Postfix) with ESMTP id 03FB11000F3; Wed, 30 Jan 2013 09:34:15 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1ee6h1de0h1202h1e76h1d1ah1d2ah1082kzz8275bhz2dh2a8h668h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h1155h) Received: from mail39-co1 (localhost.localdomain [127.0.0.1]) by mail39-co1 (MessageSwitch) id 135953845337815_9381; Wed, 30 Jan 2013 09:34:13 +0000 (UTC) Received: from CO1EHSMHS004.bigfish.com (unknown [10.243.78.219]) by mail39-co1.bigfish.com (Postfix) with ESMTP id 06E4FE004A; Wed, 30 Jan 2013 09:34:13 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO1EHSMHS004.bigfish.com (10.243.66.14) with Microsoft SMTP Server (TLS) id 14.1.225.23; Wed, 30 Jan 2013 09:34:12 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-001.039d.mgd.msft.net (10.84.1.13) with Microsoft SMTP Server (TLS) id 14.2.318.3; Wed, 30 Jan 2013 09:34:12 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r0U9Y4u3008978; Wed, 30 Jan 2013 02:34:06 -0700 From: Anson Huang To: Subject: [PATCH 1/2] ARM i.MX6: Add regulator delay support Date: Wed, 30 Jan 2013 17:33:44 -0500 Message-ID: <1359585224-11304-1-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130130_043417_118810_4BEDA837 X-CRM114-Status: UNSURE ( 8.19 ) X-CRM114-Notice: Please train this message. X-Spam-Score: 0.6 (/) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (0.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [216.32.180.188 listed in list.dnswl.org] 3.2 DATE_IN_FUTURE_12_24 Date: is 12 to 24 hours after Received: date -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: dong.aisheng@linaro.org, linux@arm.linux.org.uk, shawn.guo@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org For ANATOP LDOs, vddcpu, vddsoc and vddpu have step time settings in the misc2 register, need to add necessary step time info for these three LDOs, then regulator driver can add necessary delay based on these settings. offset 0x170: bit [24-25]: vddcpu bit [26-27]: vddpu bit [28-29]: vddsoc field definition: 0'b00: 64 cycles of 24M clock; 0'b01: 128 cycles of 24M clock; 0'b02: 256 cycles of 24M clock; 0'b03: 512 cycles of 24M clock; Signed-off-by: Anson Huang --- arch/arm/boot/dts/imx6q.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index d6265ca..a2e977d 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -480,6 +480,9 @@ anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <0>; anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; @@ -494,6 +497,9 @@ anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <9>; anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <26>; + anatop-delay-bit-width = <2>; anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; @@ -508,6 +514,9 @@ anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <18>; anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>;