From patchwork Sat Feb 2 17:25:50 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 2084551 Return-Path: X-Original-To: patchwork-linux-arm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) by patchwork1.kernel.org (Postfix) with ESMTP id 39E493FD2B for ; Sat, 2 Feb 2013 17:30:28 +0000 (UTC) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1U1gsf-00020A-Fe; Sat, 02 Feb 2013 17:27:57 +0000 Received: from mail-pa0-f43.google.com ([209.85.220.43]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1U1grw-0001Jy-2r for linux-arm-kernel@lists.infradead.org; Sat, 02 Feb 2013 17:27:12 +0000 Received: by mail-pa0-f43.google.com with SMTP id bh2so460270pad.16 for ; Sat, 02 Feb 2013 09:27:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=zq3WthXpFAVRi4EgKaqUgTo2llzVHUqIMlf3PJC43CU=; b=fJlJpO7c4nAcYLCyZCEdXQbL/eSjkgTOUtOxvpcEFGzh7RTqfNyK2iQx+2bW9x6TIj fwZvZLqCn6Jycu+Zk83s0aoZgvevu2Oi1B+GVSte8W+zvqh4Mgxo2baPqLAHLCXvVmhR kYdyoXoNNMMGo30PGktCMRrBbhoVgIP7DxzsA5GrnLjXXSp5ghl0MPX1BrxQIOwgWYHb he0oJbv4aCoNNBNoyaFTmNXp9NQT9tAt2EqWnZIWUU2a8Oq1F6HMo4DxfPdXSzPg2nVC vXz6kg4tJfAqVEtn5WGeNOGVwCu/PD/07lY+1rz9uRmzOX1vLcvhD8YFVEOxasAnCDLq R8Pw== X-Received: by 10.68.196.133 with SMTP id im5mr42753917pbc.16.1359826031218; Sat, 02 Feb 2013 09:27:11 -0800 (PST) Received: from localhost.localdomain ([27.115.121.35]) by mx.google.com with ESMTPS id b3sm10434040pax.14.2013.02.02.09.26.58 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 02 Feb 2013 09:27:10 -0800 (PST) From: Haojian Zhuang To: shiraz.hashim@st.com, shiraz.linux.kernel@gmail.com, linux@arm.linux.org.uk, tony@atomide.com, linux-arm-kernel@lists.infradead.org, swarren@nvidia.com Subject: [PATCH v8 09/12] pinctrl: single: set function mask as optional Date: Sun, 3 Feb 2013 01:25:50 +0800 Message-Id: <1359825953-15663-10-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1359825953-15663-1-git-send-email-haojian.zhuang@linaro.org> References: <1359825953-15663-1-git-send-email-haojian.zhuang@linaro.org> X-Gm-Message-State: ALoCoQlYuLh/9dkJHRKB2FGr6NYheBQ4c4TwGLPp3aHZxKQ2Lzx3T4elqaCNfBlvohlBO+uXHc4E X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130202_122712_235109_4ED7E34C X-CRM114-Status: GOOD ( 13.11 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.220.43 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Haojian Zhuang , patches@linaro.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Since Hisilicon's pin controller is divided into two parts. One is the function mux, and the other is pin configuration. These two parts are in the different memory regions. So make pinctrl-single,function-mask as optional property. Then we can define pingroups without valid function mux that is only used for pin configuration. Signed-off-by: Haojian Zhuang --- drivers/pinctrl/pinctrl-single.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 8b9dd95..fe8f321 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -350,6 +350,9 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, int i; pcs = pinctrl_dev_get_drvdata(pctldev); + /* If function mask is null, needn't enable it. */ + if (!pcs->fmask) + return 0; func = radix_tree_lookup(&pcs->ftree, fselector); if (!func) return -EINVAL; @@ -384,6 +387,10 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, int i; pcs = pinctrl_dev_get_drvdata(pctldev); + /* If function mask is null, needn't disable it. */ + if (!pcs->fmask) + return; + func = radix_tree_lookup(&pcs->ftree, fselector); if (!func) { dev_err(pcs->dev, "%s could not find function%i\n", @@ -427,6 +434,10 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, int mux_bytes = 0; unsigned data; + /* If function mask is null, return directly. */ + if (!pcs->fmask) + return -ENOTSUPP; + list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { frange = list_entry(pos, struct pcs_gpiofunc_range, node); if (pin >= frange->offset + frange->npins @@ -969,10 +980,17 @@ static int pcs_probe(struct platform_device *pdev) PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, "register width not specified\n"); - PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask, - "function register mask not specified\n"); - pcs->fshift = ffs(pcs->fmask) - 1; - pcs->fmax = pcs->fmask >> pcs->fshift; + ret = of_property_read_u32(np, "pinctrl-single,function-mask", + &pcs->fmask); + if (!ret) { + pcs->fshift = ffs(pcs->fmask) - 1; + pcs->fmax = pcs->fmask >> pcs->fshift; + } else { + /* If mask property doesn't exist, function mux is invalid. */ + pcs->fmask = 0; + pcs->fshift = 0; + pcs->fmax = 0; + } ret = of_property_read_u32(np, "pinctrl-single,function-off", &pcs->foff);